Display apparatus and gate-driver-on-array circuit

1. A display apparatus having a display area and a peripheral area, comprising:

a plurality of gate lines;

a plurality of data lines;

an insulating layer between the plurality of gate lines and the plurality of data lines;

a gate-driver-on-array circuit in the peripheral area comprising N numbers of shift register units for respectively outputting a plurality of gate scanning signals to the plurality of gate lines;

a plurality of multiplexers; and

a plurality of clock terminals;

wherein an n-th shift register unit of the N numbers of shift register units comprises an input port for receiving an input signal from an output port of a m-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p-th shift register unit through a reset signal line, 1≤m<n<p≤N; and

at least one of the input signal line and the reset signal line comprises a first segment in a same layer as the plurality of gate lines, and a second segment in a same layer as the plurality of data lines; and

the first segment and the second segment are electrically connected to each other through a via extending through the insulating layer;

wherein the N numbers of shift register units are in a first region of the peripheral area;

the input signal line for the n-th shift register unit comprises a first input signal line segment in a same layer as the plurality of gate lines, and a second input signal line segment in a same layer as the plurality of data lines, the first input signal line segment and the second input signal line segment electrically connected to each other through a via extending through the insulating layer; and

the reset signal line for the n-th shift register unit comprises a first reset signal line segment in a same layer as the plurality of gate lines, and a second reset signal line segment in a same layer as the plurality of data lines, the first reset signal line segment and the second reset signal line segment electrically connected to each other through a via extending through the insulating layer;

wherein each of the plurality of clock terminals is electrically connected to one of the plurality of data lines;

each of the plurality of clock terminals is electrically connected to one of the plurality of multiplexers through a connection line;

the connection line is in a same layer as the plurality of gate lines, the first input signal line segment, and the first reset signal line segment; and

the connection line crosses over the second input signal line segment and the second reset signal line segment.

2. The display apparatus of claim 1 , wherein the plurality of multiplexers are adjacent to the display area;

the first region is adjacent to the plurality of multiplexers and on a side of the plurality of multiplexers distal to the display area; and

the plurality of clock terminals are on a side of the N numbers of shift register units in the first region distal to the plurality of multiplexers.

3. The display apparatus of claim 1 , wherein the N numbers of shift register units are in a second region of the peripheral area;

the input signal line for the n-th shift register unit comprises a first input signal line segment in a same layer as the plurality of gate lines, and a second input signal line segment in a same layer as the plurality of data lines, the first input signal line segment and the second input signal line segment electrically connected to each other through a via extending through the insulating layer; and

the reset signal line is an integral signal line in a same layer as the plurality of gate lines.

4. The display apparatus of claim 1 , wherein the N numbers of shift register units are in a second region of the peripheral area;

the reset signal line for the n-th shift register unit comprises a first reset signal line segment in a same layer as the plurality of gate lines, and a second reset signal line segment in a same layer as the plurality of data lines, the first reset signal line segment and the second reset signal line segment electrically connected to each other through a via extending through the insulating layer; and

the input signal line is an integral signal line in a same layer as the plurality of gate lines.

5. The display apparatus of claim 1 , wherein the display area has a non-rectangular and non-square shape.

6. The display apparatus of claim 1 , wherein the display area has a substantially circular shape.

7. The display apparatus of claim 1 , wherein m is (n−1), and p is (n+1).

8. The display apparatus of claim 1 , wherein the display apparatus is a smart watch.

9. The display apparatus of claim 1 , wherein the gate-driver-on-array circuit in the peripheral area comprises N1 numbers of shift register units in a first region of the peripheral area, and N2 numbers of shift register units in a second region of the peripheral area;

wherein an n1-th shift register unit of the N1 numbers of shift register units comprises an input port for receiving an input signal from an output port of a m1-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p1-th shift register unit through a reset signal line, 1≤m1<n1<p1≤N1;

an n2-th shift register unit of the N2 numbers of shift register units comprises an input port for receiving an input signal from an output port of a m2-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p2-th shift register unit through a reset signal line, 1≤m2<n2<p2≤N2;

the input signal line for the n1-th shift register unit comprises a first input signal line segment in a same layer as the plurality of gate lines, and a second input signal line segment in a same layer as the plurality of data lines, the first input signal line segment and the second input signal line segment electrically connected to each other through a via extending through the insulating layer;

the reset signal line for the n1-th shift register unit comprises a first reset signal line segment in a same layer as the plurality of gate lines, and a second reset signal line segment in a same layer as the plurality of data lines, the first reset signal line segment and the second reset signal line segment electrically connected to each other through a via extending through the insulating layer; and

one of the input signal line and the reset signal line for the n2-th shift register unit comprises a first signal line segment in a same layer as the plurality of gate lines, and a second signal line segment in a same layer as the plurality of data lines, the first signal line segment and the second signal line segment electrically connected to each other through a via extending through the insulating layer.

10. The display apparatus of claim 9 , wherein the input signal line for the n2-th shift register unit comprises a first input signal line segment in a same layer as the plurality of gate lines, and a second input signal line segment in a same layer as the plurality of data lines, the first input signal line segment and the second input signal line segment electrically connected to each other through a via extending through the insulating layer; and

the reset signal line in the second region is an integral signal line in a same layer as the plurality of gate lines.

11. The display apparatus of claim 9 , wherein the gate-driver-on-array circuit in the peripheral area further comprises N3 numbers of shift register units in a third region of the peripheral area, and N4 numbers of shift register units in a fourth region of the peripheral area;

wherein an n3-th shift register unit of the N3 numbers of shift register units comprises an input port for receiving an input signal from an output port of a m3-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p3-th shift register unit through a reset signal line, 1≤m3<n3<p3≤N3;

an n4-th shift register unit of the N4 numbers of shift register units comprises an input port for receiving an input signal from an output port of a m4-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p4-th shift register unit through a reset signal line, 1≤m4<n4<p4≤N4;

the input signal line for the n3-th shift register unit comprises a third input signal line segment in a same layer as the plurality of gate lines, and a fourth input signal line segment in a same layer as the plurality of data lines, the third input signal line segment and the fourth input signal line segment electrically connected to each other through a via extending through the insulating layer;

the reset signal line for the n3-th shift register unit comprises a third reset signal line segment in a same layer as the plurality of gate lines, and a fourth reset signal line segment in a same layer as the plurality of data lines, the third reset signal line segment and the fourth reset signal line segment electrically connected to each other through a via extending through the insulating layer; and

one of the input signal line and the reset signal line for the n4-th shift register unit comprises a third signal line segment in a same layer as the plurality of gate lines, and a fourth signal line segment in a same layer as the plurality of data lines, the third signal line segment and the fourth signal line segment electrically connected to each other through a via extending through the insulating layer.

12. The display apparatus of claim 11 , wherein the input signal line for the n2-th shift register unit comprises a first input signal line segment in a same layer as the plurality of gate lines, and a second input signal line segment in a same layer as the plurality of data lines, the first input signal line segment and the second input signal line segment electrically connected to each other through a via extending through the insulating layer;

the input signal line for the n4-th shift register unit comprises a third input signal line segment in a same layer as the plurality of gate lines, and a fourth input signal line segment in a same layer as the plurality of data lines, the third input signal line segment and the fourth input signal line segment electrically connected to each other through a via extending through the insulating layer;

the reset signal line in the second region is an integral signal line in a same layer as the plurality of gate lines; and

the reset signal line in the fourth region is an integral signal line in a same layer as the plurality of gate lines.

13. The display apparatus of claim 11 , wherein the first region, the second region, the third region, and the fourth region are around a periphery of the display area.

14. The display apparatus of claim 13 , further comprising a rapid discharger adjacent to the display area; and

each of the second region and the fourth region is adjacent to the rapid discharger and on a side of the rapid discharger distal to the display area.

15. A display apparatus having a display area and a peripheral area, comprising:

a plurality of gate lines;

a plurality of data lines;

an insulating layer between the plurality of gate lines and the plurality of data lines;

a gate-driver-on-array circuit in the peripheral area comprising N numbers of shift register units for respectively outputting a plurality of gate scanning signals to the plurality of gate lines;

a plurality of multiplexers; and

a plurality of clock terminals;

wherein an n-th shift register unit of the N numbers of shift register units comprises an input port for receiving an input signal from an output port of a m-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p-th shift register unit through a reset signal line, 1≤m<n<p≤N; and

at least one of the input signal line and the reset signal line comprises a first segment in a same layer as the plurality of gate lines, and a second segment in a same layer as the plurality of data lines; and

the first segment and the second segment are electrically connected to each other through a via extending through the insulating layer;

wherein each of the plurality of clock terminals is electrically connected to one of the plurality of data lines;

each of the plurality of clock terminals is electrically connected to one of the plurality of multiplexers through a connection line;

the connection line is in a same layer as the plurality of gate lines, the first input signal line segment, the first reset signal line segment, the third input signal line segment, and the third reset signal line segment;

the connection line of each of the plurality of clock terminals adjacent to the first region crosses over the second input signal line segment and the second reset signal line segment; and

the connection line of each of the plurality of clock terminals adjacent to the third region crosses over the fourth input signal line segment and the fourth reset signal line segment;

wherein the gate-driver-on-array circuit in the peripheral area comprises N1 numbers of shift register units in a first region of the peripheral area, and N2 numbers of shift register units in a second region of the peripheral area;

wherein an n1-th shift register unit of the N1 numbers of shift register units comprises an input port for receiving an input signal from an output port of a m1-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p1-th shift register unit through a reset signal line, 1≤m1<n1<p1≤N1;

an n2-th shift register unit of the N2 numbers of shift register units comprises an input port for receiving an input signal from an output port of a m2-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p2-th shift register unit through a reset signal line, 1≤m2<n2<p2≤N2;

the input signal line for the n1-th shift register unit comprises a first input signal line segment in a same layer as the plurality of gate lines, and a second input signal line segment in a same layer as the plurality of data lines, the first input signal line segment and the second input signal line segment electrically connected to each other through a via extending through the insulating layer;

the reset signal line for the n1-th shift register unit comprises a first reset signal line segment in a same layer as the plurality of gate lines, and a second reset signal line segment in a same layer as the plurality of data lines, the first reset signal line segment and the second reset signal line segment electrically connected to each other through a via extending through the insulating layer; and

one of the input signal line and the reset signal line for the n2-th shift register unit comprises a first signal line segment in a same layer as the plurality of gate lines, and a second signal line segment in a same layer as the plurality of data lines, the first signal line segment and the second signal line segment electrically connected to each other through a via extending through the insulating layer;

wherein the gate-driver-on-array circuit in the peripheral area further comprises N3 numbers of shift register units in a third region of the peripheral area, and N4 numbers of shift register units in a fourth region of the peripheral area;

wherein an n3-th shift register unit of the N3 numbers of shift register units comprises an input port for receiving an input signal from an output port of a m3-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p3-th shift register unit through a reset signal line, 1≤m3<n3<p3≤N3;

an n4-th shift register unit of the N4 numbers of shift register units comprises an input port for receiving an input signal from an output port of a m4-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p4-th shift register unit through a reset signal line, 1≤m4<n4<p4≤N4;

the input signal line for the n3-th shift register unit comprises a third input signal line segment in a same layer as the plurality of gate lines, and a fourth input signal line segment in a same layer as the plurality of data lines, the third input signal line segment and the fourth input signal line segment electrically connected to each other through a via extending through the insulating layer;

the reset signal line for the n3-th shift register unit comprises a third reset signal line segment in a same layer as the plurality of gate lines, and a fourth reset signal line segment in a same layer as the plurality of data lines, the third reset signal line segment and the fourth reset signal line segment electrically connected to each other through a via extending through the insulating layer; and

one of the input signal line and the reset signal line for the n4-th shift register unit comprises a third signal line segment in a same layer as the plurality of gate lines, and a fourth signal line segment in a same layer as the plurality of data lines, the third signal line segment and the fourth signal line segment electrically connected to each other through a via extending through the insulating layer;

wherein the first region, the second region, the third region, and the fourth region are around a periphery of the display area.

16. The display apparatus of claim 15 , wherein the plurality of multiplexers are adjacent to the display area;

each of the first region and the third region is adjacent to the plurality of multiplexers and on a side of the plurality of multiplexers distal to the display area;

the plurality of clock terminals adjacent to the first region are on a side of the N1 numbers of shift register units in the first region distal to the plurality of multiplexers; and

the plurality of clock terminals adjacent to the third region are on a side of the N3 numbers of shift register units in the third region distal to the plurality of multiplexers.

17. The display apparatus of claim 15 , further comprising a fan-out area adjacent to the plurality of clock terminals, and on a side of the plurality of clock terminals distal to the plurality of multiplexers.