Semiconductor device including switch cells
A semiconductor device is provided. The semiconductor device includes a first switch and second switch cells that are disposed on a substrate and spaced apart from each other; a first metal line that is electrically connected to the first switch cell; a second metal line that is electrically connected to the second switch cell; a third metal line that is interposed between the first metal line and the second metal line; a first global metal line that at least partially overlaps the first switch cell and the second switch cell in a plan view, and electrically connects the first metal line and the second metal line; and a second global metal line that is adjacent to the first global metal line in the plan view, and is electrically connected to the third metal line.
1. A semiconductor device comprising:
a first switch cell and a second switch cell that are disposed on a substrate and spaced apart from each other along a first direction and a second direction that is perpendicular to the first direction;
a first metal line that is electrically connected to the first switch cell and extends in the second direction;
a second metal line that is electrically connected to the second switch cell and extends in the second direction;
a third metal line that is interposed between the first metal line and the second metal line and extends in the second direction;
a first global metal line that extends in the first direction, at least partially overlaps the first switch cell and the second switch cell in a plan view, and electrically connects the first metal line and the second metal line, the first global metal line being configured to receive a power supply voltage; and
a second global metal line that extends in the first direction, is adjacent to the first global metal line in the second direction in the plan view, and is electrically connected to the third metal line, the second global metal line being configured to receive a ground voltage.
2. The semiconductor device of claim 1 , further comprising:
a first stack via that is electrically connected to the first metal line and the first global metal line;
a second stack via that is electrically connected to the second metal line and the first global metal line; and
a third stack via that is electrically connected to the third metal line and the second global metal line.
3. The semiconductor device of claim 2 , further comprising:
a first via that is electrically connected to the first metal line and the first switch cell; and
a second via that is electrically connected to the second metal line and the second switch cell.
4. The semiconductor device of claim 1 , further comprising:
a ground line that extends in the first direction below the third metal line in the plan view; and
a third via that is electrically connected to the third metal line and the ground line.
5. The semiconductor device of claim 1 , further comprising a fourth metal line and a fifth metal line extending in the second direction,
wherein the first switch cell is configured to output a virtual voltage to the fourth metal line, and
wherein the second switch cell is configured to output the virtual voltage through the fifth metal line.
6. The semiconductor device of claim 5 , further comprising:
a fourth via that is electrically connected to the first switch cell and the fourth metal line; and
a fifth via that is electrically connected to the second switch cell and the fifth metal line.
7. The semiconductor device of claim 1 , wherein the second global metal line does not overlap the first switch cell and the second switch cell in the plan view.
8. The semiconductor device of claim 1 , wherein the first switch cell comprises one or more first transistors formed on a plurality of first N-wells that extend in the first direction and are adjacent in the second direction, and
wherein the second switch cell comprises one or more second transistors formed on one or more second N-wells that extend in the first direction and are adjacent in the second direction.
9. The semiconductor device of claim 1 , wherein the first metal line, the second metal line and the third metal line are formed at a first level from the substrate, and
wherein the first global metal line and the second global metal line are formed at a second level from the substrate.
10. The semiconductor device of claim 1 , wherein the first switch cell and the second switch cell are based on a P-channel metal-oxide-semiconductor (PMOS) transistor.
11. The semiconductor device of claim 10 , further comprising:
a tap cell that is formed in an N-well adjacent to the first switch cell or the second switch cell in the second direction; and
a sixth via that is electrically connected to the tap cell and the first metal line.
12. A semiconductor device comprising:
a first switch cell and a second switch cell that are disposed on a substrate and spaced apart from each other;
a first global metal line that extends in a first direction and at least partially overlaps the first switch cell and the second switch cell in a plan view, the first global metal line being configured to supply a power supply voltage to the first switch cell via a first metal line that extends in a second direction that intersects the first direction and the second switch cell via a second metal line that extends in the second direction; and
a second global metal line that extends in the first direction and is adjacent to the first global metal line in the second direction, the second global metal line being configured to supply a ground voltage to standard cells formed on the substrate,
wherein the second switch cell and the first switch cell are formed over different wells formed in the substrate.
13. The semiconductor device of claim 12 ,
wherein the first metal line intersects the first switch cell in the plan view,
wherein the second metal line intersects the second switch cell in the plan view, and
wherein the semiconductor device further comprises a third metal line that is interposed between the first metal line and the second metal line, extends in the second direction, and is electrically connected to the second global metal line.
14. The semiconductor device of claim 13 , further comprising:
a first stack via electrically that is connected to the first metal line and the first global metal line;
a second stack via electrically that is connected to the second metal line and the first global metal line; and
a third stack via electrically that is connected to the third metal line and the second global metal line.
15. The semiconductor device of claim 13 , further comprising:
a first via electrically that is connected to the first metal line and the first switch cell; and
a second via electrically that is connected to the second metal line and the second switch cell.
16. The semiconductor device of claim 12 , further comprising a fourth metal line and a fifth metal line that extend in the second direction,
wherein the first switch cell is configured to output a virtual voltage through the fourth metal line, and
wherein the second switch cell is configured to output the virtual voltage through the fifth metal line.
17. The semiconductor device of claim 12 , wherein the second global metal line does not overlap the first switch cell and the second switch cell in the plan view.
18. A semiconductor device comprising:
a first switch cell including a plurality of first transistors formed on a plurality of first N-wells, the plurality of first N-wells extending in a first direction on a substrate along a second direction perpendicular to the first direction;
a second switch cell including a plurality of second transistors formed on a plurality of second N-wells, the plurality of second N-wells extending in the first direction on the substrate along the second direction;
a first global metal line that extends in the first direction and at least partially overlaps the first switch cell and the second switch cell in a plan view, the first global metal line being configured to apply a power supply voltage to the first switch cell via a first metal line that extends in the second direction and the second switch cell via a second metal line that extends in the second direction; and
a second global metal line that extends in the first direction and is adjacent to the first global metal line in the second direction, the second global metal line being configured to apply a ground voltage to standard cells formed on the substrate.
19. The semiconductor device of claim 18 , further comprising:
a first metal line that extends in the second direction, intersects the first switch cell, and is electrically connected to the first switch cell and the first global metal line;
a second metal line that extends in the second direction, intersects the second switch cell, and is electrically connected with the second switch cell and the first global metal line; and
a third metal line that is interposed between the first metal line and the second metal line, extends in the second direction, and is electrically connected to the second global metal line.
20. The semiconductor device of claim 19 , further comprising:
a first stack via that is electrically connected to the first metal line and the first global metal line;
a second stack via that is electrically connected to the second metal line and the first global metal line; and
a third stack via that is electrically connected to the third metal line and the second global metal line.