IP Library › Granted Patent US 10,628,546
Granted Patent B1
US 10,628,546 · App. 16/024,481 · Granted Apr 21, 2020

Method and system for automatically extracting layout design patterns for custom layout design reuse through interactive recommendations

Inventors: Regis Colwell (Gibsonia, PA); Wangyang Zhang (Allison Park, PA); Elias L. Fallon (Allison Park, PA); David White (San Jose, CA); Jose A. Martinez (Pittsburgh, PA); Rong Chang Yan (New Kensington, PA)
Assignee: Cadence Design Systems, Inc.
G06F17/5072G06N5/04G06N20/00G06F2217/12
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,628,546
App. No.
16/024,481
Granted
Apr 21, 2020
Kind
B1
Abstract

Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations.

Claims (52)

1. A method, comprising:

loading electronic designs, the electronic designs comprising historical circuit schematics and corresponding historical physical layouts;

implementing a machine learning process, wherein the machine learning process generates a plurality of different trained predictors from features and labels in the electronic designs, the plurality of different trained predictors for generating predictions to a plurality of routing steps, by:

extracting features from historical circuit schematics and historical physical layouts in the electronic designs;

extracting labels from the historical circuit schematics and the historical physical layouts in the electronic designs; and

training a plurality of different predictors from different combinations of the features and the labels; and

generating a recommended physical layout for a circuit schematic of a new electronic design using two or more of the plurality of different trained predictors generated using the machine learning process.

2. The method of claim 1 , wherein the features and labels correspond to a trained model, the trained model combined with user parameters to form the plurality of different trained predictors.

3. The method of claim 1 , wherein the plurality of different predictors are partially trained using a common set of historical circuit schematics and a common set of historical physical layouts, and the plurality of different predictors are further trained using user specific circuit schematics and user specific historical physical layouts, the common set of historical circuit schematics and the common set of historical physical layouts being used for training predictors for a plurality of users, and the user specific circuit schematics and the user specific historical physical layouts being used only for the respective user.

4. The method of claim 1 , wherein the features are extracted for pairs of devices in the electronic designs, the labels are extracted for the pairs of devices, and at least one of the plurality of different trained predictors generate a recommendation pertaining to whether a pair of devices are placed on a same row in a physical layout.

5. The method of claim 1 , wherein a non-linear transformation is performed on a feature or a label.

6. The method of claim 1 , further comprising:

(a) selecting a row comprising a plurality of devices;

(b) placing the row at a physical layout position using at least one of the plurality of different trained predictors;

(c) creating routing shapes for the row; and

(d) repeating (a)-(c) when there are more devices to place.

7. The method of claim 1 , wherein feature data is processed by a decision module that determines at least one of (a) whether to place devices on a same row; (b) which row to place above or below another row; or (c) connections for devices in a row.

8. A computer program product embodied on a non-transitory computer readable medium, the computer readable medium having stored thereon a sequence of instructions which, when executed by a processor cause a set of acts, the set of acts comprising:

loading electronic designs, the electronic designs comprising historical circuit schematics and corresponding historical physical layouts;

implementing a machine learning process, wherein the machine learning process generates a plurality of different trained predictors from features and labels in the electronic designs, the plurality of different trained predictors for generating predictions to a plurality of routing steps, by:

extracting features from historical circuit schematics and historical physical layouts in the electronic designs;

extracting labels from the historical circuit schematics and the historical physical layouts in the electronic designs; and

training predictors from different combinations of the features and the labels; and

generating a recommended physical layout for a circuit schematic of a new electronic design using two or more of the plurality of different trained predictors generated using the machine learning process.

9. The computer program product of claim 8 , wherein the features and labels correspond to a trained model, the trained model combined with user parameters to form the plurality of different trained predictors.

10. The computer program product of claim 8 , wherein the predictors are partially trained using a common set of historical circuit schematics and a common set of historical physical layouts, and the predictors are further trained using user specific circuit schematics and user specific historical physical layouts, the common set of historical circuit schematics and the common set of historical physical layouts being used for training predictors for a plurality of users, and the user specific circuit schematics and the user specific historical physical layouts being used only for the respective user.

11. The computer program product of claim 8 , wherein the features are extracted for pairs of devices in the electronic designs, the labels are extracted for the pairs of devices, and at least one of the plurality of different trained predictors generate a recommendation pertaining to whether a pair of devices are placed on a same row in a physical layout.

12. The computer program product of claim 8 , wherein a non-linear transformation is performed on a feature or a label.

13. The computer program product of claim 8 , wherein the set of acts further comprise:

(a) selecting a row comprising a plurality of devices;

(b) placing the row at a physical layout position using at least one of the plurality of different trained predictors;

(c) creating routing shapes for the row; and

(d) repeating (a)-(c) when there are more devices to place.

14. The computer program product of claim 8 , wherein feature data is processed by a decision module that determines at least one of (a) whether to place devices on a same row; (b) which row to place above or below another row; or (c) connections for devices in a row.

15. A system for implementing design data for electronic designs, comprising:

a memory for storing a sequence of instructions; and

a processor that executes sequence of instructions to cause a set of acts, the set of acts comprising:

loading electronic designs, the electronic designs comprising historical circuit schematics and corresponding historical physical layouts;

implementing a machine learning process, wherein the machine learning process generates a plurality of different trained predictors from features and labels in the electronic designs, the plurality of different trained predictors for generating predictions to a plurality of routing steps, by:

extracting features from historical circuit schematics and historical physical layouts in the electronic designs;

extracting labels from the historical circuit schematics and the historical physical layouts in the electronic designs; and

training a plurality of different predictors from different combinations of the features and the labels; and

generating a recommended physical layout for a circuit schematic of a new electronic design using two or more of the plurality of different trained predictors generated using the machine learning process.

16. The system of claim 15 , wherein the features and labels correspond to a trained model, the trained model combined with user parameters to form the plurality of different trained predictors.

17. The system of claim 15 , wherein the plurality of different predictors are partially trained using a common set of historical circuit schematics and a common set of historical physical layouts, and the plurality of different predictors are further trained using user specific circuit schematics and user specific historical physical layouts, the common set of historical circuit schematics and the common set of historical physical layouts being used for training predictors for a plurality of users, and the user specific circuit schematics and the user specific historical physical layouts being used only for the respective user.

18. The system of claim 15 , wherein the features are extracted for pairs of devices in the electronic designs, the labels are extracted for the pairs of devices, and at least one of the plurality of different trained predictors generate a recommendation pertaining to whether a pair of devices are placed on a same row in a physical layout.

19. The system of claim 18 , wherein a non-linear transformation is performed on a feature or a label.

20. The system of claim 15 , wherein the set of acts further comprise:

(a) selecting a row comprising a plurality of devices;

(b) placing the row at a physical layout position using at least one of the plurality of different trained predictors;

(c) creating routing shapes for the row; and

(d) repeating (a)-(c) when there are more devices to place.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2018
From: COLWELL, REGIS; ZHANG, WANGYANG; FALLON, ELIAS L.; WHITE, DAVID; MARTINEZ, JOSE A.; YAN, RONG CHANG
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 046244/0946 →
Cited By (9)
US 12,254,258 US 12,346,432 US 12,417,610 US 12,614,017 US 12,626,046 US 12,632,638 US 12,645,858 US 12,664,347 US 12,730,959