Display device using a simultaneous emission driving method and pixel included in the display device
A display device includes a display panel including a plurality of pixels, and a panel driver that generates a scan signal, a global signal, and data signals, and provides first and second power supply voltages to the display panel. Each pixel includes a first transistor between one of data line and a first node, the first transistor receiving the scan signal at a gate of the first transistor, a second transistor to transfer the first power supply voltage in response to the global signal, a driving transistor between the second transistor and a second node, the driving transistor having a gate connected to the first node, an organic light emitting diode between the second node and the second power supply voltage, and a storage capacitor between the first node and the second node. The driving transistor and the second transistor are different ones of P-type and N-type transistors.
1. A display device, comprising:
a display panel including a plurality of scan lines, a plurality of data lines, a common emission control line, and a plurality of pixels connected to the scan lines, the data lines and the common emission control line; and
a panel driver to generate a scan signal sequentially provided to the scan lines, to generate data signals provided to the data lines, to generate a global signal provided to the common emission control line, and to provide a first power supply voltage and a second power supply voltage to the display panel,
wherein each of the plurality of pixels includes:
a first transistor connected between one of the data lines and a first node, the first transistor receiving the scan signal at a gate of the first transistor;
a second transistor to transfer the first power supply voltage in response to the global signal, the first power supply voltage having a first voltage level or a second voltage level higher than the first voltage level;
a driving transistor connected between the second transistor and a second node, the driving transistor having a gate connected to the first node;
an organic light emitting diode connected between the second node and a line of the second power supply voltage, the second power supply voltage having a third voltage level higher than the first voltage level and lower than the second voltage level; and
a storage capacitor connected between the first node and the second node,
wherein the driving transistor is one of N-type or P-type transistor and the second transistor is another of N-type or P-type transistor, and
wherein, in a writing period, the first power supply voltage has the first voltage level, the scan signal has a turn-on level, and the global signal has a turn-off level.
2. The display device as claimed in claim 1 , wherein:
the driving transistor is an N-type metal oxide semiconductor (MOS) transistor, and
the second transistor is a P-type MOS transistor.
3. The display device as claimed in claim 2 , wherein each frame of the display device includes:
an initialization period in which a voltage of the first node and a voltage of the second node are initialized,
a compensation period in which a threshold voltage of the driving transistor is compensated,
the writing period in which the data signals are sequentially written to the pixels on a row-by-row basis, and
a simultaneous emission period in which all the pixels simultaneously emit light based on the data signals.
4. The display device as claimed in claim 3 , wherein the panel driver inverts, at every predetermined number of frames, an order of outputting the scan signal in the writing period.
5. The display device as claimed in claim 4 , wherein the panel driver sequentially provides the scan signal in a first order from a first scan line to a last scan line in the writing period of a first frame, and sequentially provides the scan signal in a second order opposite to the first order from the last scan line to the first scan line in the writing period of a second frame.
6. The display device as claimed in claim 3 , wherein, in the initialization period, the first power supply voltage has the first voltage level, and the scan signal and the global signal have a turn-on level.
7. The display device as claimed in claim 3 , wherein, in the compensation period, the first power supply voltage has the second voltage level, and the scan signal and the global signal have a turn-on level.
8. The display device as claimed in claim 3 , wherein, in the simultaneous emission period, the first power supply voltage has the second voltage level, the scan signal has a turn-off level, and the global signal has a turn-on level.
9. The display device as claimed in claim 3 , wherein the panel driver provides a predetermined reference voltage to the data lines in the initialization period and the compensation period.
10. The display device as claimed in claim 3 , wherein each of an initialization operation in the initialization period and a compensation operation in the compensation period is performed simultaneously to all the pixels.
11. The display device as claimed in claim 2 , wherein the first transistor is a P-type MOS transistor.
12. The display device as claimed in claim 2 , wherein the first transistor is an N-type MOS transistor.
13. The display device as claimed in claim 12 , wherein:
a turn-on level of the scan signal is a high voltage level, and
a turn-on level of the global signal is a low voltage level.
14. The display device as claimed in claim 13 , wherein a swing width of the global signal is less than a swing width of the scan signal.
15. The display device as claimed in claim 14 , wherein a voltage high level of the global signal is lower than the high voltage level of the scan signal.
16. A pixel, comprising:
a first transistor connected between a data line and a first node, the first transistor receiving a scan signal at a gate of the first transistor;
a second transistor configured to transfer a first power supply voltage in response to a global signal, the first power supply voltage having a first voltage level or a second voltage level higher than the first voltage level;
a driving transistor connected between the second transistor and a second node, the driving transistor having a gate connected to the first node;
an organic light emitting diode connected between the second node and a line of a second power supply voltage, the second power supply voltage having a voltage level higher than the first voltage level and lower than the second voltage level; and
a storage capacitor connected between the first node and the second node,
wherein the driving transistor is one of N-type or P-type transistor and the second transistor is another of N-type or P-type transistor, and
wherein, in a writing period, the first power supply voltage has the first voltage level, the scan signal has a turn-on level, and the global signal has a turn-off level.
17. The pixel as claimed in claim 16 , wherein:
the driving transistor is an N-type metal oxide semiconductor (MOS) transistor, and
the first transistor and the second transistor are P-type MOS transistors.
18. The pixel as claimed in claim 17 , wherein the driving transistor is implemented with one of an oxide thin film transistor (TFT), a low temperature poly-silicon (LTPS) TFT, and a low temperature polycrystalline oxide (LTPO) TFT.
19. The pixel as claimed in claim 16 , wherein:
the driving transistor and the first transistor are N-type MOS transistors, and
the second transistor is a P-type MOS transistor.