Integrated circuit die with in-chip heat sink
A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.
1. An integrated circuit die comprising:
a die body having an upper surface and a lower surface, the lower surface having a plurality of bond pads for establishing electrical connection with circuitry within the die body;
a first circuit disposed in the die body and electrically coupled to at least one of the bond pads, the first circuit configured to operate at a first temperature;
a second circuit disposed in the die body and electrically coupled to at least one of the bond pads, the second circuit configured to operate at a second temperature that is less than the first temperature; and
an in-chip heat sink having a ring-shape and an orientation extending between the upper surface and the lower surface, the in-chip heat sink separating the first circuit from the second circuit.
2. The integrated circuit die of claim 1 , wherein the in-chip heat sink comprises:
vias and lines formed in metals layers of the die body.
3. The integrated circuit die of claim 2 , wherein the in-chip heat sink comprises at least one metal layer that is also in the first circuit.
4. The integrated circuit die of claim 1 , wherein the in-chip heat sink circumscribes the first circuit.
5. The integrated circuit die of claim 1 , wherein interconnect circuitry coupled to the first circuit passes through the in-chip heat sink.
6. The integrated circuit die of claim 1 further comprising:
a first dummy metal island disposed in the die body proximate the first circuit and separated from the second circuit by the in-chip heat sink; and
a second dummy metal island; and
a via connecting the first dummy metal island to the second dummy metal island.
7. The integrated circuit die of claim 6 , wherein the first dummy metal island is in direct contact with the in-chip heat sink.
8. The integrated circuit die of claim 1 , wherein the upper surface of the die body further comprises:
a plurality of metal filled recesses.
9. The integrated circuit die of claim 8 , wherein at least one of the metal filled recesses is above or in direct contact with the in-chip heat sink.
10. The integrated circuit die of claim 1 , wherein at least one of the bond pads is in direct contact with the in-chip heat sink.
11. An integrated circuit chip package comprising:
a package substrate having a top side and a bottom side; and
a first integrated circuit (IC) die coupled to the top side of the package substrate by first solder connections, the first IC die comprising:
a die body having an upper surface and a lower surface, the lower surface having a plurality of bond pads for establishing electrical connection with circuitry within the die body;
a first circuit disposed in the die body and electrically coupled to at least one of the bond pads, the first circuit configured to operate at a first temperature;
a second circuit disposed in the die body and electrically coupled to at least one of the bond pads, the second circuit configured to operate at a second temperature that is less than the first temperature; and
an in-chip heat sink having a ring-shape and an orientation extending between the upper surface and the lower surface, the in-chip heat sink separating the first circuit from the second circuit.
12. The integrated circuit chip package of claim 11 further comprising:
a heat sink coupled to the bottom side of the package substrate, the heat sink conductively coupled by a via formed through the package substrate and contacting, through some of the first solder connections, the in-chip heat sink.
13. The integrated circuit chip package of claim 11 further comprising:
a second IC die coupled to first IC by second solder connections, the second IC die having an in-chip heat sink coupled to the first IC by some of the second solder connections.
14. The integrated circuit chip package of claim 13 , wherein the in-chip heat sink of the second IC die extends to an upper surface of the second IC die.
15. The integrated circuit chip package of claim 14 , wherein the in-chip heat sink of the second IC die is electrically floating.
16. The integrated circuit chip package of claim 13 further comprising:
a cover mounted over an upper surface of the second IC die, the cover;
a thermal interface material disposed in contact with a contact pad terminating the in-chip heat sink at the upper surface of the second die and the cover; and
a heat sink disposed on the cover.
17. An integrated circuit chip package comprising:
a package substrate having a top side and a bottom side;
a first integrated circuit die having a first in-chip heat sink; and
a second integrated circuit die disposed on the top side of the package substrate, the second integrated circuit die having a first circuitry and a second circuitry separated by a second in-chip heat sink, the second in-chip heat sink coupled to the first in-chip heat sink through one or more solder connections.
18. The integrated circuit chip package of claim 17 , wherein the second integrated circuit die further comprise:
a first circuit disposed in the second integrated circuit die, the first circuit configured to operate at a first temperature;
a second circuit disposed in the second integrated circuit die and separated from the first circuit by the second in-chip heat sink, the second circuit configured to operate at a second temperature that is less than the first temperature.
19. The integrated circuit chip package of claim 17 , wherein the first in-chip heat sink is electrically floating and defines part of a highly conductive heat transfer path out through an upper surface of the second IC die.
20. The integrated circuit chip package of claim 17 , wherein the second in-chip heat sink is coupled by solder connections to the package substrate forming a highly conductive heat transfer path out through a lower surface of the second IC die.