Three-dimensional memory device having vertical semiconductor channels including source-side boron-doped pockets and methods of making the same
A three-dimensional semiconductor device includes source-level material layers including a doped semiconductor source contact layer including boron atoms and n-type dopant atoms, an alternating stack of insulating layers and electrically conductive layers located over the source-level material layers, memory stack structures vertically extending through the alternating stack in which each of the memory stack structures comprises a memory film and a vertical semiconductor channel. Each vertical semiconductor channel includes a first region in which n-type dopants have a higher atomic concentration than boron atoms and a second region overlying the first region that includes boron atoms at a higher atomic concentration than n-type dopant atoms to provide a p-n junction at an interface with the first region. Boron atoms in the source-level p-doped layer and an underlying source-level sacrificial layer that is replaced with an n-doped source contact layer yields a sharp p-n junction at the source-select gate electrode layer.
1. A three-dimensional semiconductor device, comprising:
source-level material layers including a source contact layer and located over a substrate, wherein the source contact layer comprises a doped semiconductor material comprising boron atoms and n-type dopant atoms;
an alternating stack of insulating layers and electrically conductive layers located over the source-level material layers; and
memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel,
wherein each of the vertical semiconductor channels comprises a first region in which n-type dopants have a higher atomic concentration than boron atoms and a second region overlying the first region and including boron atoms at a higher atomic concentration than n-type dopant atoms to provide a p-n junction at an interface with the first region.
2. The three-dimensional semiconductor device of claim 1 , wherein each of the vertical semiconductor channels comprises a third region overlying the second region and vertically extending at least from a second bottommost one of the electrically conductive layers to a topmost one of the electrically conductive layers.
3. The three-dimensional semiconductor device of claim 1 , wherein the source-level material layers comprise an upper source-level semiconductor layer contacting a top surface of the source contact layer and including n-type dopant atoms at an atomic concentration in a range from 1.0×10 20 /cm 3 to 2.0×10 21 /cm 3 .
4. The three-dimensional semiconductor device of claim 3 , wherein the source-level material layers comprise a lower source-level semiconductor layer contacting a bottom surface of the source contact layer and having a net p-type doping and including boron atoms at an atomic concentration in a range from 1.0×10 20 /cm 3 to 2.0×10 21 /cm 3 .
5. The three-dimensional semiconductor device of claim 1 , wherein the source-level material layers comprise a lower source-level semiconductor layer contacting a bottom surface of the source contact layer and including n-type dopant atoms at an atomic concentration in a range from 1.0×10 20 /cm 3 to 2.0×10 21 /cm 3 .
6. The three-dimensional semiconductor device of claim 5 , wherein the source-level material layers comprise an upper source-level semiconductor layer contacting a top surface of the source contact layer and having a net p-type doping and including boron atoms at an atomic concentration in a range from 1.0×10 20 /cm 3 to 2.0×10 21 /cm 3 .
7. The three-dimensional semiconductor device of claim 1 , further comprising a source-select-level conductive layer overlying the source contact layer and comprising another doped semiconductor material, wherein each second region vertically extends above a horizontal plane including a top surface of the source-select-level conductive layer.
8. The three-dimensional semiconductor device of claim 7 , wherein a maximum atomic concentration of boron atoms in the second regions is in a range from 1.0×10 19 /cm 3 to 1.0×10 20 /cm 3 .
9. The three-dimensional semiconductor device of claim 1 , wherein the source contact layer has a net n-type doping and includes n-type dopant atoms at an atomic concentration in a range from 2.0×10 20 /cm 3 to 3.0×10 21 /cm 3 .
10. The three-dimensional semiconductor device of claim 1 , wherein each of the memory films comprises:
a charge storage layer including a charge trapping material; and
a tunneling dielectric contacting the charge storage layer and a respective one of the vertical semiconductor channels.
11. The three-dimensional semiconductor device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a respective strip shape extending substantially parallel to the top surface of the substrate;
the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and the plurality of semiconductor channels including the vertical semiconductor channels, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.