Nanowire transistor structure and nanowire inverter structure
A nanowire transistor structure includes a substrate. A first nanowire is suspended on the substrate. A first gate line crosses and surrounds the first nanowire. The first gate line includes a first end and a second end. A second gate line crosses and surrounds the first nanowire. The second gate line includes a third end and a fourth end. An interlayer dielectric encapsulates the first end, the second end, the third end and the fourth end. A first distance between the first end and the first nanowire is smaller than a third distance between the third end and the first nanowire.
1. A transistor structure, comprising:
a substrate;
a first nanowire disposed on the substrate;
a first gate line crossing and surrounding the first nanowire, wherein the first gate line has a first end and a second end;
a second gate line crossing and surrounding the first nanowire, wherein the second gate line has a third end and a fourth end;
a third gate line crossing and surrounding the first nanowire, wherein the first gate line is disposed between the second gate line and the third gate line, the third gate line comprises a fifth end and a sixth end, and wherein there is not any gate line between the first gate line and the second gate line, and there is not any gate line between the first gate line and the third gate line; and
an interlayer dielectric layer encapsulating the first end, the second end, the third end and the fourth end; wherein a first distance between the first end and the first nanowire is smaller than a third distance between the third end and the first nanowire, and the first distance is smaller than a fifth distance between the fifth end and the first nanowire.
2. The transistor structure of claim 1 , wherein a second distance between the second end and the first nanowire equals a fourth distance between the fourth end and the first nanowire.
3. The transistor structure of claim 1 , wherein a second distance between the second end and the first nanowire is smaller than a fourth distance between the fourth end and the first nanowire.
4. The transistor structure of claim 1 , wherein the first end and the third end are disposed at the same side of the first nanowire.
5. The transistor structure of claim 1 , wherein a second distance between the second end and the first nanowire equals a sixth distance between the sixth end and the first nanowire.
6. The transistor structure of claim 1 , wherein a second distance between the second end and the first nanowire is smaller than a sixth distance between the sixth end and the first nanowire.
7. The transistor structure of claim 1 , wherein the first gate line overlapping the first nanowire forms a gate structure.
8. The transistor structure of claim 7 , wherein the interlayer dielectric layer comprises tensile stress, and the gate structure is a gate structure of an N-type transistor.
9. The transistor structure of claim 7 , wherein the interlayer dielectric layer comprises compressive stress, and the gate structure is a gate structure of a P-type transistor.
10. The transistor structure of claim 1 , wherein the substrate comprises a top surface, a vertical direction is perpendicular to the top surface, and the transistor structure further comprises a second nanowire disposed on the substrate, and the second nanowire aligned with the first nanowire along the vertical direction.