Efficient interface and transport mechanism for binding bindless shader programs to run-time specified graphics pipeline configurations and objects

1. A method for binding instructions to a graphical processing unit (GPU) comprising:

receiving a bindlessly compiled instruction at the GPU;

interpreting the bindlessly compiled instruction at runtime to identify a needed conversion;

generating a conversion information based on the bindlessly compiled instruction and needed conversion;

converting the bindlessly compiled instruction according to the conversion information to generate a bound format instruction; and

executing the bound format instruction.

2. The method of claim 1 , wherein, interpreting the bindlessly compiled instruction at runtime to identify a needed conversion comprises:

recognizing, by a WARP sequencer when the bindlessly compiled instruction should be converted to correspond to an API-specified GPU hardware configuration.

3. The method of claim 2 , wherein the WARP sequencer comprises an instruction pipeline having a top of instruction pipeline configured to interpret the bindlessly compiled instruction and generate the conversion information.

4. The method of claim 1 , wherein converting the bindlessly compiled instruction according to the conversion information to generate a bound format instruction comprises:

receiving, at a processing engine, the bindlessly compiled instruction and the conversion information; and

generating, using a format conversion unit of the processing engine, the bound format instruction using the bindlessly compiled instruction and the conversion information.

5. The method of claim 4 , wherein the format conversion unit operates in parallel with at least one of an integer or a floating point unit of the processing engine.

6. The method of claim 1 , wherein the conversion information comprises at least one of a render target format, a render target layout, or a texture format.

7. The method of claim 6 , further comprising:

providing the bindlessly compiled instruction and the conversion information to a load store unit (LSU); and

mapping a shader output layout to a buffer layout.

8. The method of claim 7 , wherein mapping the shader output layout to a buffer layout comprises at least one of providing a default value for a missing component or discarding an extra component.

9. A GPU comprising:

a fixed-function unit;

a WARP sequencer configured to receive a bindlessly compiled instruction and generate a conversion information based on the bindlessly compiled instruction and the fixed-function unit; and

a processing engine configured to receive the bindlessly compiled instruction and generate a bound format instruction based on the bindlessly compiled instruction and the conversion information.

10. The GPU of claim 9 , wherein the processing engine comprises using a format conversion unit, wherein the format conversion unit is configured to:

receive the bindlessly compiled instruction and the conversion information; and

generate a bound format instruction using the bindlessly compiled instruction and the conversion information.

11. The GPU of claim 9 , wherein the fixed-function unit comprises a render buffer.

12. The GPU of claim 9 , wherein the fixed-function unit comprises a rasterization subsystem.

13. The GPU of claim 9 , wherein the fixed-function unit comprises a load store unit.

14. The GPU of claim 13 , wherein the conversion information comprises a render target layout.

15. The GPU of claim 14 , wherein the load store unit is configured to generate a table for receiving updates from a shader operating on the GPU and provide an output to a render target according to the render target layout when the shader operation has completed.

16. The GPU of claim 15 , wherein the load store unit is further configured to provide a default value to the render target for a missing value that was not provided by the shader.

17. The GPU of claim 15 , wherein the load store unit is further configured to discard a value provided by the shader that is not required by the render target format.

18. The GPU of claim 9 , wherein the conversion information comprises a render target format.

19. The GPU of claim 9 , wherein the conversion information comprises a texture format.

20. The GPU of claim 9 , wherein the WARP sequencer comprises a table of render target formats.

21. The GPU of claim 9 , wherein the WARP sequencer comprises an instruction pipeline having a top of instruction pipeline configured to interpret the bindlessly compiled instruction and generate the conversion information.

22. A method for binding instructions to a graphical processing unit (GPU) comprising:

receiving a bindlessly compiled instruction at the GPU;

interpreting, by a WARP sequencer of the GPU, the bindlessly compiled instruction at runtime to identify a needed conversion;

generating, by the WARP sequencer, a conversion information based on the bindlessly compiled instruction and needed conversion;

providing, by the WARP sequencer, the bindlessly compiled instruction and the conversion information to a processing engine;

converting, by a format conversion unit of the processing engine, the bindlessly compiled instruction according to the conversion information to generate a bound format instruction; and

executing, by the processing engine, the bound format instruction.

23. The method of claim 22 , wherein the WARP sequencer comprises an instruction pipeline having a top of instruction pipeline configured to interpret the bindlessly compiled instruction and generate the conversion information.

24. The method of claim 22 , wherein the conversion information comprises at least one of a render target format, a render target layout, or a texture format.

25. The method of claim 24 , further comprising:

providing, by the WARP sequencer, the bindlessly compiled instruction and the conversion information to a load store unit (LSU); and

mapping, by the LSU, a shader output layout to a buffer layout.

26. The method of claim 25 , wherein mapping the shader output layout to a buffer layout comprises at least one of providing a default value for a missing component or discarding an extra component.