SOT-MRAM and method for writing data thereof
A semiconductor device includes a line driving unit connected to a memory cell array, a switch unit including first and second output terminals electrically connected to the memory cell array through a plurality of bit lines and a plurality of source lines, and a power supply unit outputting a precharge voltage and a source voltage to the first and second output terminals. The power supply unit includes a negative voltage generation unit that charge-shares the precharge voltage to be charged with a first voltage and discharges the first voltage to one side to generate a negative voltage on the other side.
1. A semiconductor device comprising:
a line driving unit connected to a memory cell array;
a switch unit comprising first and second output terminals electrically connected to the memory cell array through a plurality of bit lines and a plurality of source lines; and
a power supply unit outputting a precharge voltage and a source voltage to the first and second output terminals, wherein the power supply unit comprises a negative voltage generation unit that charge-shares the precharge voltage to be charged with a first voltage and discharges the first voltage to one side to generate a negative voltage on the other side.
2. The semiconductor device of claim 1 , wherein the switch unit switch-connects a pair of the bit line and the source line among the bit lines and the source lines and the first and second output terminals to each other in response to input data.
3. The semiconductor device of claim 1 , wherein the power supply unit outputs the negative voltage to the second output terminal when a drain voltage is output to the first output terminal.
4. The semiconductor device of claim 1 , wherein the negative voltage generation unit comprises:
a charge-share switch connected to the first output terminal;
a charge capacitor connected to the first output terminal through the charge-share switch;
first and second discharge transistors respectively connected to a first node located at the one side and the second output terminal; and
an output transistor connected between a second node located at the other side and the second output terminal.
5. The semiconductor device of claim 4 , wherein the charge-share switch charge-shares the precharge voltage output to the first output terminal with the charge capacitor in response to a first enable signal provided from the line driving unit.
6. The semiconductor device of claim 4 , wherein the first discharge transistor discharges the first voltage to a common ground through the first node in response to a second enable signal provided from the line driving unit.
7. The semiconductor device of claim 6 , wherein the second discharge transistor discharges the source voltage output to the second output terminal to the common ground in response to the second enable signal provided from the line driving unit.
8. The semiconductor device of claim 4 , further comprising a third discharge transistor connected to the second node, wherein the third discharge transistor discharges a negative voltage generated during a previous write operation to a common ground through the second node in response to an erase signal provided from the line driving unit.
9. The semiconductor device of claim 2 , wherein the switch unit further comprises:
a first application switch switch-connecting the first output terminal connected to one of the bit line and the source line in the pair of the bit line and the source line to the other of the bit line and the source line in the pair of the bit line and the source line in response to the input data; and
a second application switch switch-connecting the second output terminal to the one of the bit line and the source line.
10. The semiconductor device of claim 9 , wherein the memory cell array comprises a memory cell comprising a magnetic tunneling junction (MTJ) disposed between the pair of the bit line and the source line, and the memory cell comprises a read word line and a write word line, which are respectively connected to gates of first and second transistors that connect the magnetic tunneling junction to the read and write word lines.
11. The semiconductor device of claim 10 , wherein the line driving unit selects the read word line, senses a current flowing to a corresponding source line from the bit line through the magnetic tunneling junction, amplifies the sensed current, and reads storage data stored in the memory cell.
12. The semiconductor device of claim 11 , wherein the line driving unit generates a write signal according to a difference between the storage data and the input data after selecting the write word line.
13. The semiconductor device of claim 12 , wherein the negative voltage generation unit outputs the negative voltage to the second output terminal in response to the write signal.
14. A method for writing data of a semiconductor device, comprising:
allowing a negative voltage generation unit to charge-share a precharge voltage output to a first output terminal from a power supply unit and a charge capacitor to be charged with a first voltage based on the precharge voltage;
allowing the negative voltage generation unit to discharge the first voltage through a first node located at one side of the charge capacitor; and
allowing the negative voltage generation unit to output a negative voltage generated on a second node located at the other side of the charge capacitor to a second output terminal based on the discharge of the first voltage.
15. The method of claim 14 , wherein the charging comprises allowing the negative voltage generation unit to connect the first output terminal to the charge capacitor in response to a first enable signal provided from a line driving unit.
16. The method of claim 15 , wherein the discharging comprises allowing the negative voltage generation unit to connect the second node to a common ground in response to an erase signal provided from the line driving unit.
17. The method of claim 15 , wherein the discharging comprises allowing the negative voltage generation unit to connect the first node to a common ground in response to a second enable signal provided from the line driving unit.
18. The method of claim 17 , wherein the discharging comprises allowing the negative voltage generation unit to connect the second node to the second output terminal in response to the second enable signal.
19. The method of claim 14 , further comprising allowing first and second application switches of the semiconductor device, which are connected to the first and second output terminals, to switch-connect the first and second output terminals connected to a pair of a bit line and a source line among a plurality of bit lines and a plurality of source lines to each other in response to input data applied thereto.
20. The method of claim 15 , wherein the outputting comprises allowing the line driving unit to generate a third enable signal based on a difference between storage data stored in a memory cell and input data that are to be written;
allowing the line driving unit to generate a write signal based on whether the third enable signal is generated when a write word line connected to the memory cell is selected; and
allowing the negative voltage generation unit to connect the second node to the second output terminal in response to the write signal provided from the line driving unit.