Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.
1. A method for fabricating semiconductor device, comprising:
providing a substrate having a memory region and a periphery region;
forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench;
forming a first liner, a second liner, and a third liner in the first trench and the second trench;
performing a surface treatment process to lower stress of the third liner; and
planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.
2. The method of claim 1 , further comprising:
forming the first trench and the second trench on the memory region and a third trench in the substrate on the periphery region, wherein a width of the third trench is greater than a width of the second trench;
forming the first liner, the second liner, and the third liner in the first trench, the second trench, and the third trench; and
planarizing the third liner, the second liner, and the first liner to form the first isolation structure, the second isolation structure, and a third isolation structure.
3. The method of claim 2 , further comprising;
forming a fourth liner on the third liner in the second trench and the third trench;
forming a fifth liner on the fourth liner in the second trench and the third trench;
forming a sixth liner on the fifth liner in the third trench; and
planarizing the sixth liner, the fifth liner, the fourth liner, the third liner, the second liner, and the first liner to form the first isolation structure, the second isolation structure, and the third isolation structure.
4. The method of claim 3 , wherein the third liner and the fourth liner comprise different materials.
5. The method of claim 3 , wherein the third liner comprises silicon nitride and the fourth liner comprises silicon oxide.
6. The method of claim 3 , wherein the third liner and the fifth liner comprise a same material.
7. The method of claim 6 , wherein the third liner and the fifth liner comprise silicon nitride.
8. The method of claim 1 , further comprising performing an in-situ steam generation (ISSG) process to form the first liner.
9. The method of claim 1 , further comprising performing an atomic layer deposition (ALD) process to form the second liner.
10. The method of claim 1 , wherein the first liner and the second liner comprise silicon oxide.
11. The method of claim 1 , wherein the surface treatment process comprises a plasma treatment process.