Memory device and method of manufacturing the same
A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.
1. A memory device comprising:
a first electrode line extending on a substrate in a first direction;
a second electrode line on the first electrode line and extending in a second direction that is different from the first direction; and
a memory cell located at an intersection of and between the first electrode line and the second electrode line, the memory cell including a selection device, an intermediate electrode, and a variable resistance layer that are sequentially stacked,
wherein a width of the variable resistance layer is less than a width of the intermediate electrode, and a spacer is disposed on a side of the variable resistance layer,
wherein a sidewall of the memory cell has an angle greater than 90° with respect to a top surface of the substrate, and
wherein a top portion of the intermediate electrode in contact with the variable resistance layer is recessed.
2. The memory device of claim 1 , wherein a width of the memory cell gradually decreases from a lower portion of the memory cell toward an upper portion of the memory cell.
3. The memory device of claim 1 , wherein the variable resistance layer becomes gradually narrower toward an upper portion of the variable resistance layer.
4. The memory device of claim 1 , wherein the spacer surrounds the side of the variable resistance layer, and an outer side surface of the spacer constitutes a portion of a side surface of the memory cell.
5. The memory device of claim 4 , wherein the width of the variable resistance layer is controlled according to a width of the spacer.
6. The memory device of claim 1 , wherein an outer side surface of the spacer is self-aligned with side surfaces of the selection device and the intermediate electrode.
7. The memory device of claim 1 , wherein there are a plurality of the first electrode lines, a plurality of the second electrode lines, and a plurality of the memory cells,
the memory device further comprising:
a first insulating layer extending in the first direction and disposed between the plurality of the first electrode lines; and
a second insulating layer disposed between the plurality of the memory cells,
wherein the first electrode line has a first recess formed in an upper portion between the plurality of the memory cells and disposed along the first direction, and
wherein the first insulating layer has a second recess formed in an upper portion between the plurality of the memory cells and disposed along the second direction.
8. The memory device of claim 1 , wherein the intermediate electrode comprises a heating electrode in contact with a bottom surface of the variable resistance layer.
9. The memory device of claim 1 , wherein the memory cell comprises a lower electrode that is in contact with the first electrode line.
10. A memory device comprising:
a substrate;
a first electrode line extending on the substrate in a first direction;
a second electrode line extending on the first electrode line in a second direction that is different from the first direction; and
a memory cell located at an intersection of and between the first electrode line and the second electrode line, the memory cell including a selection device, an intermediate electrode, and a variable resistance layer that are sequentially stacked,
wherein a spacer is disposed on a side of the variable resistance layer, and an outer side surface of the spacer is self-aligned with side surfaces of the selection device and the intermediate electrode, and
wherein the selection device, the variable resistance layer, and the spacer have side surfaces having a same side surface slope such that a width of the memory cell gradually decreases from the selection device toward an upper portion of the memory cell.
11. The memory device of claim 10 , wherein a width of the variable resistance layer is less than a width of the intermediate electrode, and the spacer is disposed on a top surface of the intermediate electrode.
12. The memory device of claim 10 , wherein the intermediate electrode protrudes from the side of the variable resistance layer, and the spacer is disposed on a top surface of a protruding portion of the intermediate electrode.
13. The memory device of claim 10 , wherein the spacer surrounds the side of the variable resistance layer, and an outer side surface of the spacer constitutes a portion of a side surface of the memory cell.
14. The memory device of claim 10 , wherein a width of the variable resistance layer is controlled according to a width of the spacer.
15. A memory device comprising:
a substrate;
a first electrode line layer including first electrode lines extending on the substrate in a first direction and being spaced apart from each other;
a second electrode line layer including second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other; and
a memory cell layer including memory cells located at intersections of and between the first electrode lines and the second electrode lines, each memory cell including a selection device, an intermediate electrode, a heating electrode, and a variable resistance layer that are sequentially stacked,
wherein a width of the variable resistance layer is less than a width of the intermediate electrode, the intermediate electrode protrudes from a side of the variable resistance layer, and a spacer is disposed on a side of the variable resistance layer on a top surface of a protruding portion of the heating electrode, and
wherein a combined width of the variable resistance layer and the spacer is less than a width of the selection device.
16. The memory device of claim 15 , wherein a width of the memory cell gradually decreases from a lower portion of the memory cell toward an upper portion of the memory cell.
17. The memory device of claim 15 , wherein an outer side surface of the spacer is self-aligned with side surfaces of the selection device and the intermediate electrode.
18. The memory device of claim 15 , further comprising:
an integrated circuit layer formed on the substrate and disposed under the first electrode line layer;
a first insulating layer extending in the first direction and disposed between the first electrode lines; and
a second insulating layer disposed between the memory cells,
wherein the first electrode lines have a first recess formed in an upper portion between the memory cells and disposed along the first direction, and
wherein the first insulating layer has a second recess formed in an upper portion between the memory cells and disposed along the second direction.