Semiconductor chip including integrated security circuit

1. A method of fabricating an authentic integrated circuit, the method comprising:

forming an integrated circuit on a substrate;

placing a plurality of individual security parts on a white space of the substrate that excludes the integrated circuit, the plurality of individual security parts defining at least one security circuit, each security part being completely separated from one another and dispersed at a different white space locations of the substrate so as to separate the security circuit into segments; and

programming at least one security part among the plurality of individual security parts with key code data so as to program the at least one security circuit with a key code,

wherein the individual security parts include e-fuses.

2. The method of claim 1 further comprising:

forming multiple security circuits on the integrated circuit;

designating at least one of the multiple security circuits as a valid security circuit, while designating remaining multiple security circuits as unused security circuits; and

programming the at least one valid security circuit with a valid key code, while excluding the valid key code from the unused security circuits.

3. The method of claim 2 , wherein a false key code different from the valid key code is programmed into at least one of the unused security circuits to hinder reverse engineering efforts.

4. The method of claim 3 further comprising reading the false key code from the at least one unused security circuit to hinder reverse engineering by unauthenticated users.

5. The method of claim 2 , wherein the valid key code is segmented in parts and programmed into multiple security circuits to hinder reverse engineering efforts.

6. The method of claim 1 , wherein the plurality of individual security parts are non-erasable memory elements.

7. The method of claim 1 , wherein the plurality of individual security parts are reprogrammable memory elements.

8. The method of claim 1 , wherein a plurality of integrated circuits are co-located on a silicon wafer, and wherein each integrated circuit has at least one corresponding security circuit, and wherein each security circuit is programmed with the same key code.

9. The method of claim 1 , wherein a plurality of integrated circuits are co-located on a silicon wafer, the plurality of integrated circuits including a first integrated circuit having a first security circuit and a second integrated circuit having a second security circuit, wherein the first security circuit is programmed with a first key code and the second security circuit is programmed with a second key code different from the first key code.

10. The method of claim 1 , wherein a plurality of integrated circuits are co-located on a silicon wafer, and wherein each integrated circuit has at least one corresponding security circuit, and wherein some security circuits are programmed with the same key code and the remainder of the security circuits are programmed with a unique key code.

11. The method of claim 1 further comprising covering the at least one security circuit with an opaque layer to prevent accessing the plurality of individual security parts using penetrating light.

12. A device including an authenticate integrated circuit, the device comprising:

an integrated circuit on a substrate;

at least one security circuit segmented into at least two completely separated security parts,

wherein the at least two security parts are located at different white space locations on the substrate such that the at least one security circuit extends from a first white space location of the substrate to a second white space location located remotely from the first white space location, the white space locations excluding the integrated circuit, and

wherein at least one of the security parts includes an e-fuse having a key code programmed therein that authenticates the integrated circuit.

13. The device of claim 12 further comprising multiple security circuits located on the integrated circuit, wherein the multiple security circuits include at least one operational security circuit that stores a valid key code and at least one non-operational security circuit that excludes the valid key code.

14. The device of claim 13 , wherein a false key code is programmed into the at least one security circuit.

15. The device of claim 13 , wherein the multiple security circuits comprise at least 100 circuits.

16. The device of claim 12 , wherein the e-fuses are non-erasable memory elements.

17. The device of claim 12 , wherein the e-fuses are reprogrammable memory elements.

18. The device of claim 12 , wherein the security circuit is covered with an opaque layer comprising a material configured to at least one of block or reflect energy from penetrating therethrough.