Gate driving circuit and display panel with reset function

1. A gate driving circuit, comprising:

1 st to N th stage shift registers configured to respectively provide 1 st to N th stage scan signals to 1 st to N th gate lines of a display panel of a display device, wherein N is an integer greater than 1;

wherein an i th stage shift register of the 1 st to N th stage shift registers comprises:

a pre-charge unit that is coupled to a first node of the i th stage shift register and is configured to receive a first input signal and output a pre-charge signal to the first node;

a pull-up unit that is coupled to the first node and a second node of the i th stage shift register and is configured to output an i th stage scan signal of the 1 st to N th stage scan signals to the second node; and

a pull-down unit that is coupled to the first node and the second node and is configured to receive a pull-down control signal;

wherein i is an integer that is greater than or equal to 1 and is smaller than or equal to N, the first input signal received by the 1 st stage shift register switches from a low voltage level to a high voltage level at a first time point, and the pull-down control signal switches from a disable voltage to an enable voltage before the display panel switches from a non-display status to a display status and before the first time point.

2. The gate driving circuit of claim 1 , wherein the i th stage shift register further comprises another pull-down unit; wherein:

the pull-down unit is configured to further receive another pull-down control signal; and

the another pull-down unit is coupled to the first node and the second node and is configured to receive the pull-down control signal and the another pull-down control signal.

3. The gate driving circuit of claim 2 , wherein the pull-down control signal and the another pull-down control signal are phase inverted during a time duration before the display panel switches from the non-display status to the display status, and the time duration is greater than or equal to 50 milliseconds and is less than or equal to 1 second.

4. The gate driving circuit of claim 2 , wherein the pull-down unit comprises:

a fourth transistor, wherein a control terminal and a first terminal of the fourth transistor are configured to receive the pull-down control signal;

a fifth transistor, wherein a control terminal of the fifth transistor is configured to receive the another pull-down control signal, a first terminal of the fifth transistor is coupled to a reference voltage, and a second terminal of the fifth transistor is coupled to a second terminal of the fourth transistor;

a sixth transistor, wherein a control terminal of the sixth transistor is coupled to the first node, a first terminal of the sixth transistor is coupled to the reference voltage, and a second terminal of the sixth transistor is coupled to the second terminal of the fourth transistor;

a seventh transistor, wherein a control terminal of the seventh transistor is coupled to the second terminal of the sixth transistor, a first terminal of the seventh transistor is coupled to the reference voltage, and a second terminal of the seventh transistor is coupled to the first node; and

an eighth transistor, wherein a control terminal of the eighth transistor is coupled to the second terminal of the sixth transistor, a first terminal of the eighth transistor is coupled to the reference voltage, and a second terminal of the eighth transistor is coupled to the second node.

5. The gate driving circuit of claim 4 , wherein the another pull-down unit further comprises:

a ninth transistor, wherein a control terminal and a first terminal of the ninth transistor are configured to receive the another pull-down control signal;

a tenth transistor, wherein a control terminal of the tenth transistor is configured to receive the pull-down control signal, a first terminal of the tenth transistor is coupled to the reference voltage, and a second terminal of the tenth transistor is coupled to a second terminal of the ninth transistor;

an eleventh transistor, wherein a control terminal of the eleventh transistor is coupled to the first node, a first terminal of the eleventh transistor is coupled to the reference voltage, and a second terminal of the eleventh transistor is coupled to the second terminal of the ninth transistor;

a twelfth transistor, wherein a control terminal of the twelfth transistor is coupled to the second terminal of the eleventh transistor, a first terminal of the twelfth transistor is coupled to the reference voltage, and a second terminal of the twelfth transistor is coupled to the first node; and

a thirteenth transistor, wherein a control terminal of the thirteenth transistor is coupled to the second terminal of the eleventh transistor, a first terminal of the thirteenth transistor is coupled to the reference voltage, and a second terminal of the thirteenth transistor is coupled to the second node.

6. The gate driving circuit of claim 1 , wherein the first input signal received by the 1 st stage shift register is a starting signal.

7. The gate driving circuit of claim 1 , wherein the pull-down control signal switches from the disable voltage to the enable voltage before the display panel displays a first frame after the display device leaves a sleep mode.

8. The gate driving circuit of claim 1 , wherein the pull-down control signal switches from the disable voltage to the enable voltage before the display panel displays a first frame after the display device is powered on.

9. The gate driving circuit of claim 1 , wherein the pull-down control signal keeps at the enable voltage during a time duration before the display panel switches from the non-display status to the display status, and the time duration is greater than or equal to 50 milliseconds and is less than or equal to 1 second.

10. The gate driving circuit of claim 1 , wherein the pre-charge unit comprises:

a first transistor, wherein a control terminal of the first transistor is configured to receive the first input signal, a first terminal of the first transistor is configured to receive a forward input signal, and a second terminal of the first transistor is coupled to the first node; and

a second transistor, wherein a control terminal of the second transistor is configured to receive a second input signal, a first terminal of the second transistor is configured to receive a backward input signal, and a second terminal of the second transistor is coupled to the second terminal of the first transistor.

11. The gate driving circuit of claim 1 , wherein the pull-up unit comprises:

a third transistor, wherein a control terminal of the third transistor is configured to receive the pre-charge signal, a first terminal of the third transistor is configured to receive a clock signal, and a second terminal of the third transistor is configured to output the i th stage scan signal; and

a capacitor, wherein a first terminal of the capacitor is coupled to the control terminal of the third transistor, and a second terminal of the capacitor is coupled to the second terminal of the third transistor.

12. A gate driving circuit, comprising:

1 st to N th stage shift registers configured to respectively provide 1 st to N th stage scan signals to 1 st to N th gate lines of a display panel, wherein N is an integer greater than 1;

wherein an i th stage shift register of the 1 st to N th stage shift registers comprises:

a pre-charge unit that is coupled to a first node of the i th stage shift register and is configured to receive a first input signal and output a pre-charge signal to the first node;

a pull-up unit that is coupled to the first node and a second node of the i th stage shift register and is configured to output an i th stage scan signal of the 1 st to N th stage scan signals to the second node;

a first pull-down unit that is coupled to the first node and the second node and is configured to receive a first pull-down control signal and a second pull-down control signal; and

a second pull-down unit that is coupled to the first node and the second node and is configured to receive the first pull-down control signal and the second pull-down control signal;

wherein i is an integer that is greater than or equal to 1 and is smaller than or equal to N, the first input signal received by the 1 st stage shift register switches from a low voltage level to a high voltage level at a first time point, and at least one of the first pull-down control signal and the second pull-down control signal switches from a disable voltage to an enable voltage before the display panel switches from a non-display status to a display status and before the first time point.

13. The gate driving circuit of claim 12 , the first pull-down control signal and the second pull-down control signal are phase-inverted during a time duration before the display panel switches from the non-display status to the display status.

14. The gate driving circuit of claim 13 , wherein the time duration is greater than or equal to 50 milliseconds and is less than or equal to 1 second.

15. A display panel having a display area and a non-display area, the display panel comprising:

a substrate;

a plurality of gate lines and a plurality of data lines disposed on the substrate, the plurality of gate lines having 1 st to N th gate lines, wherein N is an integer greater than 1; and

1 st to N th stage shift registers that are disposed on the substrate and in the non-display area and are configured to respectively provide 1 st to N th stage scan signals to the 1 st to N th gate lines;

wherein an i th stage shift register of the 1 st to N th stage shift registers comprises:

a pre-charge unit that is coupled to a first node of the i th stage shift register and is configured to receive a first input signal and output a pre-charge signal to the first node;

a pull-up unit that is coupled to the first node and a second node of the i th stage shift register, and is configured to output an i th stage scan signal of the 1 st to N th stage scan signals to the second node; and

a pull-down unit that is coupled to the first node and the second node and is configured to receive a pull-down control signal;

wherein i is an integer that is greater than or equal to 1 and is smaller than or equal to N, the first input signal received by the 1 st stage shift register switches from a low voltage level to a high voltage level at a first time point, and the pull-down control signal switches from a disable voltage to an enable voltage before the display panel switches from a non-display status to a display status and before the first time point.

16. The display panel of claim 15 , wherein the 1 st to N th stage shift registers are a gate driver on array (GOA).

17. The display panel of claim 15 , wherein the i th stage shift register further comprises another pull-down unit; wherein:

the pull-down unit is configured to further receive another pull-down control signal; and

the another pull-down unit is coupled to the first node and the second node and is configured to receive the control signal and the another pull-down control signal.

18. The display panel of claim 17 , wherein the pull-down control signal and the another pull-down control signal are phase inverted during a time duration before the display panel switches from the non-display status to the display status.

19. The display panel of claim 18 , wherein the time duration is greater than or equal to 50 milliseconds and is less than or equal to 1 second.