Gate driver and display device including the same
A gate driver and a display device including the same are disclosed. The gate driver includes a plurality of stages. Each stage includes a transistor T 6 outputting an emission signal of a gate-on voltage to a node Na while a node Q is activated, a transistor T 7 outputting the emission signal of a gate-off voltage to the node Na while a node QB is activated, a Q controller controlling a voltage of the node Q depending on a clock signal ECLK 1 and a clock signal ECLK 2 that are in antiphase, and a voltage of a node Q′, a QB controller controlling a voltage of the node QB depending on the clock signal ECLK 1 , the voltage of the node Q, and the voltage of the node Q′, and a capacitor CQ connected between an input terminal of the clock signal ECLK 1 and the node Q.
1. A gate driver comprising:
a plurality of stages including K stages,
wherein a k-th stage of the plurality of stages, k being an integer less than K, includes:
a transistor T 6 configured to output an emission signal of a gate-on voltage to a node Na of the k-th stage while a node Q of the k-th stage is activated;
a transistor T 7 configured to output the emission signal of a gate-off voltage to the node Na while a node QB of the k-th stage is activated;
a Q controller configured to control a voltage of the node Q depending on a voltage of a node Q′ of the k-th stage and a clock signal ECLK 1 and a clock signal ECLK 2 which are in antiphase;
a QB controller configured to control a voltage of the node QB depending on the clock signal ECLK 1 , the voltage of the node Q, and the voltage of the node Q′; and
a capacitor CQ connected between an input terminal of the clock signal ECLK 1 and the node Q and having a first capacitance, the input terminal of the clock signal ECLK 1 being disposed in the k-th stage,
wherein a ratio of the first capacitance to a total capacitance including the first capacitance and a parasitic capacitance formed in the node Q is 50% or more.
2. The gate driver of claim 1 , wherein as the ratio of the first capacitance to the total capacitance increases while the voltage of the node Q is bootstrapped, a gate-to-source voltage of the transistor T 6 increases.
3. The gate driver of claim 2 , wherein the voltage of the node Q is bootstrapped every time the clock signal ECLK 1 of the gate-on voltage is input within a period in which the emission signal of the gate-on voltage is output.
4. The gate driver of claim 1 , wherein the k-th stage further includes a Q′ controller configured to control the voltage of the node Q′ depending on the clock signal ECLK 1 , the clock signal ECLK 2 , and the voltage of the node Q.
5. The gate driver of claim 4 , wherein the QB controller of the k-th stage includes:
a transistor T 8 configured to be switched depending on the voltage of the node Q′ and apply the clock signal ECLK 1 to a node Nb;
a transistor T 9 configured to be switched depending on the clock signal ECLK 1 and connect the node Nb to the node QB;
a transistor T 5 configured to be switched depending on the voltage of the node Q and apply the gate-off voltage to the node QB; and
a capacitor CQB connected between the node QB and an input terminal of the gate-off voltage.
6. The gate driver of claim 5 , wherein the Q′ controller of the k-th stage includes:
a transistor T 10 configured to be switched depending on the voltage of the node Q and apply the clock signal ECLK 2 to the node Q′;
a transistor T 4 configured to be switched depending on the clock signal ECLK 2 and apply the gate-on voltage to the node Q′; and
a capacitor CQ' connected between the node Q′ and the node Nb.
7. The gate driver of claim 1 , wherein the k-th stage further includes a transistor TBv including one electrode connected to the node Q and a gate electrode connected to an input terminal of the gate-on voltage,
wherein the transistor TBv is turned off while the voltage of the node Q is bootstrapped.
8. The gate driver of claim 7 , wherein the voltage of the node Q is bootstrapped every time the clock signal ECLK 1 of the gate-on voltage is input within a period in which the emission signal of the gate-on voltage is output.
9. The gate driver of claim 1 , wherein the k-th stage further includes:
a transistor T 7 a connected to one electrode of the transistor T 7 and an input terminal of the gate-off voltage and configured to be switched depending on the voltage of the node QB; and
a transistor T 11 connected to a node Nc between the transistor T 7 and the transistor T 7 a and an input terminal of the gate-on voltage and configured to be switched depending on a voltage of the node Na.
10. The gate driver of claim 1 , wherein the Q controller of the k-th stage includes:
a transistor T 1 configured to be switched depending on the clock signal ECLK 2 and apply a start signal to the node Q;
a transistor T 2 configured to be switched depending on the clock signal ECLK 1 , of which one electrode is connected to the node Q; and
a transistor T 3 configured to be switched depending on the voltage of the node Q′ and apply the gate-off voltage to the other electrode of the transistor T 2 .
11. A display device comprising:
a display panel including gate lines connected to pixels; and
a gate driver according to claim 1 , configured to generate an emission signal and supply the emission signal to the gate lines through stages.
12. The display device of claim 11 , wherein each pixel includes:
an organic light emitting diode (OLED);
a driving thin film transistor (TFT) configured to control a driving current flowing in the OLED depending on a gate-to-source voltage of the driving TFT; and
an emission TFT configured to be turned on or off in response to the emission signal and determine an emission timing of the OLED.