Semiconductor device and method of manufacturing the same
A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source select line. The semiconductor device may include word lines. The semiconductor device may include a channel layer. The semiconductor device may include a source structure. The source structure may be disposed under the source select line. The source structure may be in contact with the channel layer.
1. A method of manufacturing a semiconductor device, comprising:
forming a stack group including a first source layer, a sacrificial source layer on the first source layer, a gate insulating layer on the sacrificial source layer, a first conductive layer on the gate insulating layer, and first material layers and second material layers alternately stacked on the first conductive layer;
forming a channel layer which is extended into the first source layer while passing through the first material layers and the second material layers and is surrounded by a multilayered memory layer;
forming a first through portion which passes the first material layers and the second material layers by selectively etching the first material layers and the second material layers with a first etching material before the first conductive layer is passed through;
forming a slit which is extended from the first through portion and passes through the first conductive layer and the gate insulating layer; and
replacing the sacrificial source layer with a contact source layer through the slit, the contact source layer being in direct contact with the first source layer and the channel layer and being insulated from the first conductive layer by the gate insulating layer.
2. The method of claim 1 , wherein the stack group further includes a first passivation layer disposed between the first source layer and the sacrificial source layer, a second passivation layer and a second source layer sequentially stacked between the sacrificial source layer and the gate insulating layer, and an interface layer disposed between a stacked body of the first and second material layers and the first conductive layer.
3. The method of claim 2 , wherein the first passivation layer, the second passivation layer, the second material layers, and the interface layer are formed of an insulating material.
4. The method of claim 3 , wherein the interface layer is formed to be thinner than the second material layers and the gate insulating layer.
5. The method of claim 2 , wherein the first source layer, the second source layer, the contact source layer, and the first conductive layer are formed of doped silicon layers including first conductive type impurities.
6. The method of claim 5 , wherein the first conductive type impurities include n-type impurities.
7. The method of claim 2 , wherein the first source layer is disposed to be farthest from the first conductive layer than the second source layer and contact source layer.
8. The method of claim 2 , wherein the contact source layer is disposed between the first source layer and the second source layer.
9. The method of claim 2 , wherein the forming of the slit includes:
forming a second through portion which is connected to the first through portion and passes through the first conductive layer by etching the first conductive layer with a second etching material before the gate insulating layer is passed through;
forming a first buffer layer by oxidizing a lateral wall of the first conductive layer exposed through the second through portion; and
forming a third through portion which is connected to the second through portion and exposes the sacrificial source layer by etching the gate insulating layer, the second source layer, and the second passivation layer.
10. The method of claim 2 , wherein the second source layer is formed to be thinner than the first conductive layer and each of the first material layers and the second material layers.
11. The method of claim 2 , wherein the replacing of the sacrificial source layer with the contact source layer through the slit includes:
opening a source area between the first passivation layer and the second passivation layer by removing the sacrificial source layer exposed through the slit;
removing a part of the multilayered memory layer between the first source layer and the second source layer, and the first passivation layer and the second passivation layer so that a lateral wall of the channel layer and the first and second source layers are exposed through the source area; and
forming the contact source layer that is in direct contact with the lateral wall of the channel layer and the first and second source layers exposed through the source area.
12. The method of claim 11 , wherein in the removing of the part of the multilayered memory layer, a first ring-type recess is formed between the second source layer and the channel layer and a second ring-type recess is formed between the first source layer and the channel layer, and
the contact source layer is formed to be filled in the first and second ring-type recesses.
13. The method of claim 1 , wherein the first conductive layer is formed to be thicker than each of the first and second material layers.
14. The method of claim 1 , further comprising:
replacing the first material layers with third material layers formed of a conductive material having lower resistance than that of the first conductive layer through the slit.
15. The method of claim 1 , further comprising:
forming a source junction inside the channel layer by performing a heat treatment process so that first conductive type impurities included in the contact source layer and the first source layer are diffused into the channel layer.
16. The method of claim 15 , wherein the source junction is extended to be higher than the first conductive layer from a contact surface between a lateral wall of the channel layer and the contact source layer.
17. The method of claim 1 , further comprising:
forming a second buffer layer by oxidizing a surface of each of the contact source layer and the first source layer exposed through the slit;
forming a first doping area by injecting first conductive type impurities from a surface of the first source layer that is in contact with a bottom surface of the slit toward an inner side of the first source layer;
forming a lateral wall insulating layer on a lateral wall of the slit; and
forming a source contact line which is surrounded by the lateral wall insulating layer, is filled inside the slit, and is in contact with the first doping area while passing through the second buffer layer.
18. The method of claim 17 , further comprising:
forming a second doping area by injecting the first conductive type impurities from a lateral wall of the contact source layer that is in contact with a lateral wall of the slit toward an inner side of the contact source layer.
19. The method of claim 18 , wherein the first conductive type impurities are distributed with a first concentration inside a source structure including the contact source layer and the first source layer, are distributed with a second concentration higher than the first concentration inside the first doping area, and are distributed with a third concentration that is higher than the first concentration and is lower than the second concentration inside the second doping area.