FinFET device with non-recessed STI
A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate and a semiconductor fin on the substrate, forming a dummy gate structure on the semiconductor fin, forming a first dielectric layer on the semiconductor structure exposing an upper surface of the dummy gate structure, removing the dummy gate structure and a portion of the semiconductor fin below the dummy gate structure to form a trench that divides the semiconductor fin into a first portion and a second portion spaced apart from each other, and forming a second dielectric layer on the semiconductor structure filling the trench. The method provides a semiconductor device having a non-recessed trench isolation structure.
1. A semiconductor device, comprising:
a substrate;
a semiconductor fin on the substrate;
a first dielectric layer on the semiconductor fin;
a trench on the substrate and in the semiconductor fin and the first dielectric layer, the trench dividing the semiconductor fin into a first portion and a second portion that are spaced apart from each other;
a first gate structure and a second gate structure on opposite sides of the trench, the first gate structure being on the first portion and the second gate structure being on the second portion;
a hardmask layer on an upper surface of the first gate structure and on an upper surface of the second gate structure; and
a second dielectric layer on the first dielectric layer and on the hardmask layer, and filling the trench.
2. The semiconductor device of claim 1 , further comprising:
a spacer on sidewalls of the first gate structure and the second gate structure.
3. The semiconductor device of claim 1 , further comprising:
a first electrode and a second electrode on opposite sides of the first gate structure; and
a third electrode and a fourth electrode on opposite sides of the second gate structure.
4. The semiconductor device of claim 3 , further comprising:
a first contact, a second contact, a third contact, and a fourth contact each extending through the first dielectric layer and the second dielectric layer and connecting to the first electrode, the second electrode, the third electrode, and the fourth electrode, respectively.
5. The semiconductor device of claim 1 , wherein the trench comprises a depth in a range between 2000 angstroms and 4000 angstroms, and a first trench portion between the first portion and the second portion and a second trench portion above the first trench portion,
the first trench portion having a depth in a range between 1000 angstroms and 2000 angstroms, and the second trench portion having a depth in a range between 1000 angstroms and 2000 angstroms.
6. The semiconductor device of claim 1 , further comprising:
a trench isolation portion on the substrate and surrounding the semiconductor fin, the trench isolation portion having a bottom that is substantially flush with a bottom of the trench.
7. The semiconductor device of claim 1 , wherein the hardmask layer comprises silicon nitride.
8. The semiconductor device of claim 1 , further comprising a trench isolation layer surrounding the semiconductor fin, the trench isolation layer having a bottom that is substantially flush with a bottom of the trench.
9. The semiconductor device of claim 8 , further comprising an insulator layer disposed between the trench isolation layer and the semiconductor fin.
10. The semiconductor device of claim 9 , wherein the insulator layer comprises silicon dioxide.