Tunnel field-effect transistor with reduced subthreshold swing
A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.
1. A method for manufacturing a semiconductor device, comprising:
forming a source layer on a semiconductor substrate;
forming a channel layer on the source layer;
forming a drain layer on the channel layer;
patterning the source, channel and drain layers into at least one fin;
forming a cap layer on a lower portion of the at least one fin comprising the source layer and part of the channel layer;
forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer;
wherein the cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer; and
forming a spacer layer on an upper portion of the at least one fin comprising the drain layer and another part of the channel layer;
wherein forming the cap layer comprises epitaxially growing the cap layer on the lower portion of the at least one fin; and
wherein the spacer layer prevents epitaxial growth of the cap layer from the upper portion of the at least one fin.
2. The method according to claim 1 , wherein the cap layer comprises a III-V compound semiconductor material.
3. The method according to claim 2 , wherein the source, channel and drain layers each comprise a III-V compound semiconductor material different from the III-V compound semiconductor material of the cap layer.
4. The method according to claim 1 , wherein the cap layer has larger band gap than a band gap of the source and channel layers.
5. The method according to claim 1 , further comprising doping the source and drain layers to have opposite doping types from each other.
6. The method according to claim 1 , wherein the at least one fin extends perpendicularly with respect to a top surface of the semiconductor substrate.
7. The method according to claim 1 , wherein a thickness of the cap layer is in the range of about 1 nm to about 10 nm.
8. The method according to claim 1 , wherein the cap layer covers a tunnel junction between the source layer and the channel layer.