2-D material transistor with vertical structure
Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate with a fin thereon, wherein the fin comprises first and second sidewalls and a top surface;
depositing a first dielectric layer on the fin, wherein the first dielectric layer covers the first and second sidewalls and the top surface of the fin;
depositing a two-dimensional (2-D) material layer on the first dielectric layer;
depositing a second dielectric layer on the 2-D material layer;
depositing an electrode layer on the second dielectric layer; and
patterning the electrode layer and the second dielectric layer to form a gate stack having a length shorter than that of the 2-D material layer.
2. The method of claim 1 , wherein patterning the electrode layer and the second dielectric layer comprises etching the electrode layer and the second dielectric layer to expose a portion of the 2-D material layer over the first and second sidewalls and the top surface of the fin.
3. The method of claim 1 , further comprising:
forming a source terminal and a drain terminal on the fin, wherein the 2-D material layer over the first and second sidewalls and the top surface of the fin is between the source and drain terminals.
4. The method of claim 3 , wherein each of the source and the drain terminals comprises at least one of platinum, nickel, cobalt; tantalum; titanium; platinum, erbium, palladium, aluminum, and tungsten.
5. The method of claim 1 , wherein the 2-D material layer comprises graphene, a transition metal dichalcogenide (TMD) material, or phosphorene.
6. The method of claim 1 , wherein depositing the 2-D material layer comprises epitaxially growing the 2-D material layer on a seed layer disposed on the first dielectric layer.
7. The method of claim 1 , wherein depositing the 2-D material layer comprises growing the 2-D material layer on a liner layer disposed on the first dielectric layer.
8. The method of claim 1 ; wherein depositing the 2-D material layer comprises depositing the 2-D material layer with an aqueous solution of graphene oxide.
9. A semiconductor structure, comprising:
a substrate comprising a fin, wherein the fin comprises sidewalls and a top surface;
an insulating region disposed on the substrate and covering a bottom portion of the sidewalls of the fin;
a dielectric layer disposed on the top surface of the fin and on the sidewalls of the fin not covered by the insulating region;
a two-dimensional (2-D) material layer disposed on the dielectric layer, wherein the 2-D material layer extends over the insulating region; and
a gate stack disposed on a portion of the 2-D material layer over the top surface and sidewalls of the fin.
10. The semiconductor structure of claim 9 , wherein the gate stack is disposed on an other portion of the 2-D material layer over the insulating region.
11. The semiconductor structure of claim 9 , wherein the gate stack comprises an other dielectric layer and a gate electrode.
12. The semiconductor structure of claim 9 , further comprising a source terminal and a drain terminal disposed on the fin, wherein the source and drain terminals are on opposite sides of the gate stack.
13. The semiconductor structure of claim 9 , wherein the 2-D material layer has a thickness between about 0.5 nm and about 10 nm.
14. A semiconductor structure, comprising:
a substrate comprising first and second fins separated by an inner gate region comprising a first gate electrode;
a first two dimensional (2-D) material layer extending between a first sidewall of the first fin and a first sidewall of the second fin;
a second 2-D material layer extending between a second sidewall of the first fin and a second sidewall of the second fin, wherein the inner gate region is disposed between the first and second 2-D material layers;
a first outer gate region disposed on a portion of the first 2-D material layer opposite from the inner gate region, wherein the first outer gate region comprises the first gate electrode and a second gate electrode; and
a second outer gate region disposed on a portion of the second 2-D material layer opposite to the inner gate region, wherein the second gate region comprises the first electrode and the second gate electrode.
15. The semiconductor structure of claim 14 , wherein the inner gate region comprises the first gate electrode disposed between a first inner dielectric layer and a second inner dielectric layer.
16. The semiconductor structure of claim 15 , wherein the first inner dielectric layer is on the first 2-D material layer between the first and second fins and the second inner dielectric layer is on the second 2-D material layer between the first and second fins.
17. The semiconductor structure of claim 14 , wherein the inner gate region is shorter than the first and second outer gate regions.
18. The semiconductor structure of claim 14 , wherein the first outer gate region comprises a first outer dielectric layer on a portion of the first 2-D material layer.
19. The semiconductor structure of claim 14 , wherein the second outer gate region comprises a second outer dielectric layer on a portion of the second 2-D material layer.
20. The semiconductor structure of claim 14 , wherein the first and second gate electrodes comprise a same material and the inner gate region is shorter than the first and second outer gate regions.