Pixel circuit and image sensing system
The present application provides a pixel circuit, applied in an image sensing system. The pixel circuit is coupled to a first collection node and a second collection node. The pixel circuit includes a first capacitor; a second capacitor; a first shutter switch coupled between the first capacitor and the first collection node; a second shutter switch coupled between the second capacitor and the second collection node; a third shutter switch coupled between the second capacitor and the first collection node; a fourth shutter switch coupled between the first capacitor and the second collection node; and a common mode reset module coupled to the first capacitor and the second capacitor.
1. A pixel circuit, applied in an image sensing system, wherein the pixel circuit is coupled to a first collection node and a second collection node, characterized in that, the pixel circuit comprises:
a first capacitor;
a second capacitor;
a first shutter switch, coupled between the first capacitor and the first collection node;
a second shutter switch, coupled between the second capacitor and the second collection node;
a third shutter switch, coupled between the second capacitor and the first collection node;
a fourth shutter switch, coupled between the first capacitor and the second collection node; and
a common mode reset module, coupled to the first capacitor and the second capacitor;
wherein both of the first shutter switch and the third shutter switch are directly connected to the first collection node;
wherein both of the second shutter switch and the fourth shutter switch are directly connected to the second collection node.
2. The pixel circuit as claim 1 , characterized in that, within a first time, the first shutter switch and the second shutter switch are conducted, the third shutter switch and the fourth shutter switch are cutoff; and within a second time, the first shutter switch and the second shutter switch are cutoff, the third shutter switch and the fourth shutter switch are conducted.
3. The pixel circuit as claim 2 , characterized in that, the first time and the second time have the same time length.
4. The pixel circuit as claim 1 , characterized by, further comprising a first output module and a second output module, wherein the first output module comprises a first source follower transistor and a first read transistor, a gate of the first source follower transistor is coupled to the first capacitor, a source of the first source follower transistor is coupled to the first read transistor; the second output module comprises a second source follower transistor and a second read transistor, a gate of the second source follower transistor is coupled to the second capacitor, a source of the second source follower transistor is coupled to the second read transistor.
5. The pixel circuit as claim 1 , characterized in that, the common mode reset module comprises:
a first transistor, coupled to a first terminal of the first capacitor;
a second transistor, coupled to a first terminal of the second capacitor;
a first reset transistor, coupled between a second terminal of the first capacitor and the first terminal of the second capacitor; and
a second reset transistor, coupled between a second terminal of the second capacitor and the first terminal of the first capacitor.
6. The pixel circuit as claim 5 , characterized in that, gates of the first transistor and the second transistor receive a common mode reset signal, and gates of the first reset transistor and the second reset transistor receive a pixel reset signal.
7. The pixel circuit as claim 5 , characterized in that, when the first reset transistor and the second reset transistor are conducted, the first transistor and the second transistor are cutoff.