Engine to enable high speed context switching via on-die storage
In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.
1. A graphics multiprocessor comprising:
an instruction cache to receive a stream of instructions;
an instruction unit to dispatch instructions in the stream of instructions for execution;
a general-purpose graphics processing compute block comprising a plurality of graphics processing cores, the graphics processing cores comprising a plurality of execution units to execute the instructions;
a first shared memory communicatively coupled to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units; and
a copy engine to:
receive a signal from a scheduler indicating an initiation of a preemption process;
stop an execution of an existing context on at least a first of the plurality of execution units;
copy context state data from the existing context on the at least a first of the plurality of execution units to the first shared memory;
generate a signal to indicate that a context preemption process is complete; and
upload the context data from the first shared memory to a second memory, separate from the first shared memory.
2. The graphics multiprocessor of claim 1 , further comprising:
a scheduler to initiate a preemption process.
3. The graphics multiprocessor of claim 1 , further comprising:
a first communication fabric to communicatively couple the plurality of execution units to the first shared memory.
4. The graphics multiprocessor of claim 3 , wherein the copy engine is coupled to the first shared memory by the first communication fabric.
5. The graphics multiprocessor of claim 4 , wherein the first shared memory comprises a L3 cache.
6. The graphics multiprocessor of claim 1 , further comprising:
a second communication fabric to communicatively couple the copy engine to the second memory.
7. The graphics multiprocessor of claim 1 , the copy engine to:
copy context state data from the existing context on at least a first of the plurality of execution units to the first shared memory in parallel with executing a new context on the plurality of execution units.
8. The graphics multiprocessor of claim 1 , further comprising logic, at least partially including hardware logic, to:
restore the first shared memory.
9. The graphics multiprocessor of claim 1 , wherein the plurality of execution units and a first general register file are on a single integrated circuit.
10. An electronic device, comprising:
a central processing unit;
a graphics multiprocessor communicatively coupled to the central processing unit, comprising:
an instruction cache to receive a stream of instructions;
an instruction unit to dispatch instructions in the stream of instructions for execution;
a general-purpose graphics processing compute block comprising a plurality of graphics processing cores, the graphics processing cores comprising a plurality of execution units to execute the instructions;
a first shared memory communicatively coupled to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units; and
a copy engine to:
receive a signal from a scheduler indicating an initiation of a preemption process;
stop an execution of an existing context on the at least a first of the plurality of execution units;
copy context state data from the existing context on at least a first of the plurality of execution units to the first shared memory;
generate a signal to indicate that a context preemption process is complete; and
upload the context data from the first shared memory to a second memory, separate from the first shared memory.
11. The electronic device of claim 10 , further comprising:
a scheduler to initiate a preemption process.
12. The electronic device of claim 10 , further comprising:
a first communication fabric to communicatively couple the plurality of execution units to the first shared memory.
13. The electronic device of claim 12 , wherein the copy engine is coupled to the first shared memory by the first communication fabric.
14. The electronic device of claim 13 , wherein the first shared memory comprises a L3 cache.
15. The electronic device of claim 10 , further comprising:
a second communication fabric to communicatively couple the copy engine to the second memory.
16. The electronic device of claim 15 , the copy engine to:
copy context state data from the existing context on at least a first of the plurality of execution units to the first shared memory in parallel with executing a new context on the plurality of execution units.
17. The electronic device of claim 10 , further comprising logic, at least partially including hardware logic, to:
restore the first shared memory.
18. The electronic device of claim 10 , wherein the plurality of execution units and a first general register file are on a single integrated circuit.
19. A method comprising:
receiving, in a copy engine of a general-purpose graphics processing compute block comprising a plurality of graphics processing cores, the graphics processing cores comprising a processor having a plurality of execution units to execute the instructions a signal from a scheduler indicating an initiation of a preemption process;
stopping an execution of an existing context on the at least a first of the plurality of execution units;
copying context state data from the existing context on at least a first of the plurality of execution units to a first shared memory;
generating a signal to indicate that a context preemption process is complete; and
uploading the context data from the first shared memory to a second memory, separate from the first shared memory.
20. The method of claim 19 , further comprising:
copying context state data from an existing context on the at least a first of the plurality of execution units to the first shared memory in parallel with executing a new context on the plurality of execution units.