Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation

1. A neurosynaptic system comprising:

a neural computation unit comprising multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the multiple electronic neurons with the multiple electronic axons, wherein the neural computation unit is configured to perform a set of computations based on one or more axonal inputs and a first neural computation matrix to generate one or more neuronal outputs;

a scheduler delay buffer configured to receive and buffer the one or more axonal inputs; and

a packet router configured to:

receive one or more external inputs from an environment external to the neurosynaptic system, each external input comprising a sensory input;

transmit one or more external outputs to the environment external to the neurosynaptic system, each external output comprising a motor output;

selectively route the one or more external inputs based on a first routing permutation matrix, each external input routed to one of: the scheduler delay buffer as one of the one or more axonal inputs, or the environment external to the neurosynaptic system as one of the one or more external outputs; and

selectively route the one or more neuronal outputs based on the first routing permutation matrix, each neuronal output routed to one of: the scheduler delay buffer as an axonal input, or the environment external to the neurosynaptic system as one or the one or more external outputs;

wherein the first neural computation matrix represents a concatenation of multiple neural computation matrices implemented by multiple layers of neurosynaptic core circuits;

wherein the first routing permutation matrix represents a concatenation of multiple routing permutation matrices implemented by the multiple layers; and

wherein the multiple layers is a hybrid of a fully feed-forward configuration and a fully recurrent configuration.

2. The neurosynaptic system of claim 1 , wherein:

each neurosynaptic core circuit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the multiple neurons with the multiple axons.

3. The neurosynaptic system of claim 2 , wherein each layer further comprises an interconnection network that interconnects neurosynaptic core circuits of the layer.

4. The neurosynaptic system of claim 3 , wherein:

each neuronal output represents a neural firing of a neuron.

5. The neurosynaptic system of claim 4 , wherein:

the packet router enables inter-core routing.

6. The neurosynaptic system of claim 4 , wherein:

the scheduler delay buffer maintains at least one axonal input for a pre-determined time delay.

7. The neurosynaptic system of claim 1 , wherein:

the set of computations comprise a hybrid of feed-forward computations and recurrent computations;

the packet router is configured to:

implement one-to-one mapping if a first sum of a total number of axonal inputs buffered by the scheduler delay buffer and a total number of external outputs transmitted by the packet router is equal to a second sum of a total number of neuronal outputs generated and a total number of externals inputs received by the packet router;

implement routing fan-out if the first sum of the total number of axonal inputs buffered and the total number of external outputs transmitted is greater than the second sum of the total number of neuronal outputs generated and the total number of externals inputs received; and

implement routing fan-in if the first sum of the total number of axonal inputs buffered and the total number of external outputs transmitted is less than the second sum of the total number of neuronal outputs generated and the total number of externals inputs received.

8. The neurosynaptic system of claim 1 , wherein:

the set of computations include at least one of an auto-regressive function, a linear function, and a non-linear function.

9. The neurosynaptic system of claim 1 , wherein:

the multiple layers are interconnected.

10. A method comprising:

receiving and buffering one or more axonal inputs in a scheduler delay buffer of a neurosynaptic system;

generating one or more neuronal outputs by performing a set of computations based on the one or more axonal inputs and a first neural computation matrix utilizing a neural computation unit of the neurosynaptic system, wherein the neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the multiple electronic neurons with the multiple electronic axons;

receiving, via a packet router of the neurosynaptic system, one or more external inputs from an environment external to the neurosynaptic system, wherein each external input comprises a sensory input;

transmitting, via the packet router, one or more external outputs to the environment external to the neurosynaptic system, wherein each external output comprises a motor output;

selectively routing, via the packet router, the one or more external inputs based on a first routing permutation matrix, wherein each external input is routed to one of: the scheduler delay buffer as one of the one or more axonal inputs, or the environment external to the neurosynaptic system as one of the one or more external outputs; and

selectively routing, via the packet router, the one or more neuronal outputs based on the first routing permutation matrix, wherein each neuronal output is routed to one of: the scheduler delay buffer as an axonal input, or the environment external to the neurosynaptic system as one or the one or more external outputs;

wherein the first neural computation matrix represents a concatenation of multiple neural computation matrices implemented by multiple layers of neurosynaptic core circuits;

wherein the first routing permutation matrix represents a concatenation of multiple routing permutation matrices implemented by the multiple layers; and

wherein the multiple layers is a hybrid of a fully feed-forward configuration and a fully recurrent configuration.

11. The method of claim 10 , wherein:

each neurosynaptic core circuit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the multiple neurons with the multiple axons.

12. The method of claim 11 , wherein:

each layer further comprises an interconnection network that interconnects neurosynaptic core circuits of the layer; and

each neuronal output represents a neural firing of a neuron.

13. The method of claim 12 , wherein:

the packet router enables inter-core routing.

14. The method of claim 12 , wherein:

the scheduler delay buffer maintains at least one axonal input for a pre-determined time delay.

15. The method of claim 10 , wherein:

the set of computations comprise a hybrid of feed-forward computations and recurrent computations;

the packet router is configured to:

implement one-to-one mapping if a first sum of a total number of axonal inputs buffered by the scheduler delay buffer and a total number of external outputs transmitted by the packet router is equal to a second sum of a total number of neuronal outputs generated and a total number of externals inputs received by the packet router;

implement routing fan-out if the first sum of the total number of axonal inputs buffered and the total number of external outputs transmitted is greater than the second sum of the total number of neuronal outputs generated and the total number of externals inputs received; and

implement routing fan-in if the first sum of the total number of axonal inputs buffered and the total number of external outputs transmitted is less than the second sum of the total number of neuronal outputs generated and the total number of externals inputs received.

16. A computer program product for computing computational functions, the computer program product comprising a non-transitory computer-readable storage medium having program code embodied therewith, the program code being executable by a computer to:

receiving and buffering one or more axonal inputs in a scheduler delay buffer of a neurosynaptic system;

generating one or more neuronal outputs by performing a set of computations based on the one or more axonal inputs and a first neural computation matrix utilizing a neural computation unit of the neurosynaptic system, wherein the neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the multiple electronic neurons with the multiple electronic axons;

receiving, via a packet router of the neurosynaptic system, one or more external inputs from an environment external to the neurosynaptic system, wherein each external input comprises a sensory input;

transmitting, via the packet router, one or more external outputs to the environment external to the neurosynaptic system, wherein each external output comprises a motor output;

selectively routing, via the packet router, the one or more external inputs based on a first routing permutation matrix, wherein each external input is routed to one of: the scheduler delay buffer as one of the one or more axonal inputs, or the environment external to the neurosynaptic system as one of the one or more external outputs; and

selectively routing, via the packet router, the one or more neuronal outputs based on the first routing permutation matrix, wherein each neuronal output is routed to one of: the scheduler delay buffer as an axonal input, or the environment external to the neurosynaptic system as one or the one or more external outputs;

wherein the first neural computation matrix represents a concatenation of multiple neural computation matrices implemented by multiple layers of neurosynaptic core circuits;

wherein the first routing permutation matrix represents a concatenation of multiple routing permutation matrices implemented by the multiple layers; and

wherein the multiple layers is a hybrid of a fully feed-forward configuration and a fully recurrent configuration.