Method for forming source/drain contacts

1. A method, comprising:

providing a structure that includes:

a substrate;

a semiconductor fin; and

an epitaxial feature over the semiconductor fin, the epitaxial feature including silicon germanium (SiGe);

doping gallium (Ga) into the epitaxial feature;

performing a first annealing process at a first temperature;

depositing a conductive material including a metal over the epitaxial feature after the first annealing process; and

performing a second annealing process at a second temperature to cause reaction between the metal and the epitaxial feature.

2. The method of claim 1 , wherein the first temperature is in a range from about 400 degrees Celsius to about 600 degrees Celsius.

3. The method of claim 1 , wherein both the first and the second temperatures are in a range from about 400 degrees Celsius to about 600 degrees Celsius.

4. The method of claim 1 , further comprising:

performing a third annealing process at a third temperature higher than the first and second temperatures.

5. The method of claim 4 , after the second annealing process and before the third annealing process, further comprising:

removing unreacted portions of the conductive material.

6. The method of claim 1 , further comprising:

doping boron (B) into the epitaxial feature simultaneously with the doping of gallium.

7. The method of claim 1 , wherein Ge concentration in the SiGe ranges from about 55% to about 75%.

8. The method of claim 1 , wherein the metal includes titanium.

9. A method comprising:

providing a structure that includes:

a substrate;

a gate structure over the substrate; and

an epitaxial feature including silicon germanium (SiGe) adjacent to the gate structure;

doping gallium (Ga) ions into the epitaxial feature;

performing a first annealing process at a recrystallization temperature of the SiGe;

depositing a material including a metal over the epitaxial feature after the first annealing process;

performing a second annealing process to form a compound having at least Si and the metal over the epitaxial feature; and

performing a third annealing process to activate dopants including Ga in the epitaxial feature.

10. The method of claim 9 , further comprising:

forming a conductive plug over the compound after the performing of the third annealing process.

11. The method of claim 9 , wherein both the first and the second annealing processes are performed at temperatures ranging from about 400 degrees Celsius to about 600 degrees Celsius.

12. The method of claim 11 , wherein Ge concentration in the SiGe ranges from about 55% to about 75%.

13. The method of claim 9 , further comprising:

doping boron (B) into the epitaxial feature before the performing of the first annealing process.

14. A method for making a semiconductor structure, comprising:

providing a substrate, a semiconductor fin connected to the substrate, and an epitaxial layer disposed over the semiconductor fin;

implanting gallium (Ga) in an upper portion of the epitaxial layer; and

forming a silicide feature over and in contact with the epitaxial layer, wherein the epitaxial layer including silicon germanium (SiGe) and is in contact with the implanted upper portion.

15. The method of claim 14 , wherein the Ga is implanted in the upper portion of the epitaxial layer to a thickness of about 6 nm to 8 nm.

16. The method of claim 14 , wherein a ratio of germanium to silicon (Ge:Si) in the SiGe is greater than 1.

17. The method of claim 14 , wherein germanium (Ge) concentration in the SiGe ranges from about 55% to about 75%.

18. The method of claim 14 , wherein the upper portion of the epitaxial layer further includes boron.

19. The method of claim 14 , wherein the silicide feature includes Ge or Ga.

20. The method of claim 14 , wherein the silicide feature includes titanium silicide and is substantially free of gallium and boron.