IP Library › Granted Patent US 10,651,302
Granted Patent B2
US 10,651,302 · App. 16/015,198 · Granted May 12, 2020

Semiconductor device

Inventors: Yosuke Sakurai (Azumino, JP); Yuichi Onozawa (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/7397H01L29/0626H01L29/0684H01L29/1045H01L29/404H01L29/407
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Quick Facts
Patent No.
US 10,651,302
App. No.
16/015,198
Granted
May 12, 2020
Kind
B2
Abstract

A semiconductor device including: a semiconductor substrate; a drift region of first conductivity type that is formed in the semiconductor substrate; an accumulation region of first conductivity type that is formed above the drift region and has higher concentration than concentration of the drift region; a base region of second conductivity type that is formed above the accumulation region; and a gate trench portion that is formed extending from an upper surface of the semiconductor substrate to the drift region, passing through the base region and the accumulation region, wherein a maximum value of doping concentration of the accumulation region is greater than a maximum value of doping concentration of the base region will be provided.

Claims (45)

1. A semiconductor device comprising:

a semiconductor substrate;

a drift region of first conductivity type that is formed in the semiconductor substrate;

an accumulation region of first conductivity type that is formed above the drift region and has a higher concentration than a concentration of the drift region;

a base region of second conductivity type that is formed above the accumulation region; and

a gate trench portion that is formed extending from an upper surface of the semiconductor substrate to the drift region, passing through the base region and the accumulation region, wherein

a maximum value of a doping concentration of the accumulation region is greater than a maximum value of a doping concentration of the base region,

a doping concentration distribution of the accumulation region in a depth direction has at least one peak, and a doping concentration distribution of the base region in the depth direction has at least one peak, and

an integrated concentration that is obtained by integrating the doping concentration of the accumulation region in the depth direction of the semiconductor substrate is less than an integrated concentration that is obtained by integrating the doping concentration of the base region in the depth direction of the semiconductor substrate.

2. The semiconductor device according to claim 1 , wherein

the maximum value of the doping concentration of the accumulation region is five times the maximum value of the doping concentration of the base region or smaller.

3. The semiconductor device according to claim 1 , wherein

the maximum value of the doping concentration of the accumulation region is 1.5 times the maximum value of the doping concentration of the base region or greater.

4. The semiconductor device according to claim 1 , wherein

the doping concentration distribution of the accumulation region in the depth direction has multiple peaks; and

a doping concentration at a peak closest to the base region among the multiple peaks is lower than a doping concentration at a peak closest to the drift region.

5. The semiconductor device according to claim 1 , wherein

the doping concentration distribution of the base region in the depth direction has multiple peaks; and

a doping concentration at a peak closest to the upper surface side of the semiconductor substrate among the multiple peaks in the doping concentration distribution of the base region is higher than a doping concentration at a peak closest to the accumulation region side.

6. The semiconductor device according to claim 1 , wherein

an upper integrated concentration that is obtained by integrating the doping concentration of the base region above a center in the depth direction of the base region is more than a lower integrated concentration that is obtained by integrating the doping concentration of the base region below the center in the depth direction of the base region.

7. The semiconductor device according to claim 1 , wherein

a depth position where the doping concentration of the accumulation region takes the maximum value is closer to the drift region than a center of the accumulation region in the depth direction.

8. The semiconductor device according to claim 1 , further comprising

a dummy trench portion that is formed extending from an upper surface of the semiconductor substrate to the drift region, passing through the base region and the accumulation region, wherein

a doping concentration of a part, in the accumulation region, adjacent to the dummy trench portion is higher than a doping concentration of a part adjacent to the gate trench portion.

9. The semiconductor device according to claim 1 , wherein

a length of the accumulation region in the depth direction is smaller than or equal to a length of the base region in the depth direction.

10. The semiconductor device according to claim 1 , wherein

a length of the accumulation region in the depth direction is smaller than or equal to a length of a protruding part of the gate trench portion below a bottom end of the accumulation region.

11. The semiconductor device according to claim 1 , wherein

the accumulation region is formed in a region sandwiched by two of the gate trench portions that are lined up in a lateral direction; and

a length of the accumulation region in the depth direction is smaller than an interval in the lateral direction between central portions of the two of the gate trench portions.

12. The semiconductor device according to claim 1 , wherein

the accumulation region is formed in a region sandwiched by two of the gate trench portions that are lined up in a lateral direction; and

an integrated value that is obtained by integrating the doping concentration of the accumulation region in the lateral direction at a depth position corresponding to a peak concentration in the doping concentration distribution of the accumulation region in the depth direction is greater than half a value of a critical integrated concentration of the accumulation region.

13. The semiconductor device according to claim 1 , wherein

the gate trench portion has:

a trench that is formed extending from an upper surface of the semiconductor substrate to the drift region, passing through the base region and the accumulation region;

an insulating film that is formed on an inner wall of the trench;

a gate conductive portion that is formed, in the trench, facing the base region; and

a dummy conductive portion that is formed below the gate conductive portion and insulated from the gate conductive portion, and

at least partial region of the accumulation region is formed facing the dummy conductive portion.

14. The semiconductor device according to claim 1 , wherein

the accumulation region contacts with the drift region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2018
From: SAKURAI, YOSUKE; ONOZAWA, YUICHI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 046171/0490 →
Priority Claims (1)
JP 2016-141284 · Jul 19, 2016 · national
Continuity (2)
Continuation PCTJP2017026160 · Jul 19, 2017
Related Publication 20180301550A1 · Oct 18, 2018