Four-phase oscillator and CDR circuit

1. A clock and data recovery circuit comprising:

a first oscillator configured to output a first differential signal, the first oscillator including

a first resonator including an inductor and a capacitor coupled in parallel,

a first cross-coupled circuit in which a first pair of transistors coupled to the first resonator are cross-coupled,

a first tail current source coupled to the first pair of transistors,

first input differential pair transistors configured to receive a second differential signal, and

a second tail current source coupled to the first input differential pair transistors;

a second oscillator configured to output the second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, the second oscillator including

a second resonator including an inductor and a capacitor coupled in parallel,

a second cross-coupled circuit in which a second pair of transistors coupled to the second resonator are cross-coupled,

a third tail current source coupled to the second pair of transistors,

second input differential pair transistors configured to receive the first differential signal, and

a fourth tail current source coupled to the second input differential pair transistors;

a control circuit configured to control, based on which of a first resonant frequency at which the first resonator resonates and a second resonant frequency at which the second resonator resonates is higher, at least one of a difference between a first current value supplied from the first tail current source and a third current value supplied from the third tail current source and a difference between a second current value supplied from the second tail current source and a fourth current value supplied from the fourth tail current source;

an inverter configured to output a third differential signal inverted the phase of the second differential signal based on the change of the frequency by the control circuit;

a first phase detect circuit configured to output a first phase detect signal based on a difference between a received data signal and the first differential signal;

a second phase detect circuit configured to output a second phase detect signal based on a difference between a received data signal and the second differential signal;

a frequency detect circuit configured to compare the first phase detect signal with the second phase detect signal, and output a frequency detect signal based on a difference between the received signal and the first differential signal;

a control voltage generation circuit configured to generate a control voltage to adjust frequencies and phases of the first differential signal and the second differential signal based on the first phase detect signal and the frequency detect signal; and

a data generation circuit configured to regenerate data from the received data according to the first differential signal.

2. The clock and data recovery circuit according to claim 1 , wherein the first resonant frequency at which the first resonator resonates is different from the second resonant frequency at which the second resonator resonates.

3. The clock and data recovery circuit according to claim 2 , wherein

when the first resonant frequency is higher than the second resonant frequency, the control circuit sets the first current value higher than the third current value and sets the second current value higher than the fourth current value and sets the first current value lower than the third current value and sets the second current value lower than the fourth current value, and

when the first resonant frequency is lower than the second resonant frequency, the control circuit sets the first current value lower than the third current value and sets the second current value lower than the fourth current value and sets the first current value higher than the third current value and sets the second current value higher than the fourth current value.

4. A clock and data recovery circuit comprising:

a first oscillator configured to output a first differential signal, the first oscillator including

a first resonator including an inductor and a capacitor coupled in parallel,

a first cross-coupled circuit in which a first pair of transistors coupled to the first resonator are cross-coupled,

a first tail current source coupled to the first pair of transistors,

first input differential pair transistors configured to receive a second differential signal, and

a second tail current source coupled to the first input differential pair transistors;

a second oscillator configured to output the second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, the second oscillator including

a second resonator including an inductor and a capacitor coupled in parallel,

a second cross-coupled circuit in which a second pair of transistors coupled to the second resonator are cross-coupled,

a third tail current source coupled to the second pair of transistors,

second input differential pair transistors configured to receive the first differential signal, and

a fourth tail current source coupled to the second input differential pair transistors;

a control circuit configured to control, based on a first resonant frequency at which the first resonator resonates and a second resonant frequency at which the second resonator resonates, at least one of a difference between a first current value supplied from the first tail current source and a second current value supplied from the second tail current source and a difference between a third current value supplied from the third tail current source and a fourth current value supplied from the fourth tail current source;

an inverter configured to output a third differential signal inverted the phase of the second differential signal based on the change of the frequency by the control circuit;

a first phase detect circuit configured to output a first phase detect signal based on a difference between a received data signal and the first differential signal;

a second phase detect circuit configured to output a second phase detect signal based on a difference between a received data signal and the second differential signal;

a frequency detect circuit configured to compare the first phase detect signal with the second phase detect signal, and output a frequency detect signal based on a difference between the received signal and the first differential signal;

a control voltage generation circuit configured to generate a control voltage to adjust frequencies and phases of the first differential signal and the second differential signal based on the first phase detect signal and the frequency detect signal; and

a data generation circuit configured to regenerate data from the received data according to the first differential signal.

5. The clock and data recovery circuit according to claim 4 , wherein when the control circuit performs at least one of setting the first current value higher than the second current value and setting the third current value higher than the fourth current value and performs at least one of setting the second current value higher than the first current value and setting the fourth current value higher than the third current value.

6. The clock and data recovery circuit according to claim 4 , wherein the first input differential pair transistors are coupled in parallel to the first pair of transistors and the second input differential pair transistors are coupled in parallel to the second pair of transistors.

7. The clock and data recovery circuit according to claim 6 , wherein

the first resonator is coupled between a first output terminal and a second output terminal,

the second resonator is coupled between a third output terminal and a fourth output terminal,

the first pair of transistors include a first transistor coupled to the first output terminal and a second transistor coupled to the second output terminal,

the first input differential pair transistors include a third transistor which is coupled in parallel to the first transistor and is coupled to the fourth output terminal and a fourth transistor which is coupled in parallel to the second transistor and is coupled to the third output terminal,

the second pair of transistors include a fifth transistor coupled to the third output terminal and a sixth transistor coupled to the fourth output terminal, and

the second input differential pair transistors include a seventh transistor which is coupled in parallel to the fifth transistor and is coupled to the first output terminal and an eighth transistor which is coupled in parallel to the sixth transistor and is coupled to the second output terminal.

8. A clock and data recovery circuit comprising:

a four-phase oscillator configured to output a first differential signal and a second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, the four-phase oscillator including

a first oscillator configured to output a first differential signal, the first oscillator including

a first resonator including an inductor and a capacitor coupled in parallel,

a first cross-coupled circuit in which a first pair of transistors coupled to the first resonator are cross-coupled,

a first tail current source coupled to the first pair of transistors,

first input differential pair transistors configured to receive a second differential signal, and

a second tail current source coupled to the first input differential pair transistors;

a second oscillator configured to output the second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, the second oscillator including

a second resonator including an inductor and a capacitor coupled in parallel,

a second cross-coupled circuit in which a second pair of transistors coupled to the second resonator are cross-coupled,

a third tail current source coupled to the second pair of transistors,

second input differential pair transistors configured to receive the first differential signal, and

a fourth tail current source coupled to the second input differential pair transistors; and

a control circuit configured to change the frequency of the first and second differential signals by controlling at least one of a difference between a first current value supplied from the first tail current source and a third current value supplied from the third tail current source and a difference between a second current value supplied from the second tail current source and a fourth current value supplied from the fourth tail current source

an inverter configured to output a third differential signal inverted the phase of the second differential signal based on the change of the frequency by the control circuit;

a first phase detect circuit configured to output a first phase detect signal based on a difference between a received data signal and the first differential signal;

a second phase detect circuit configured to output a second phase detect signal based on a difference between a received data signal and the second differential signal;

a frequency detect circuit configured to compare the first phase detect signal with the second phase detect signal, and output a frequency detect signal based on a difference between the received signal and the first differential signal;

a control voltage generation circuit configured to generate a control voltage to adjust frequencies and phases of the first differential signal and the second differential signal based on the first phase detect signal and the frequency detect signal;

a data generation circuit configured to regenerate data from the received data according to the first differential signal.

9. A clock and data recovery circuit comprising:

a four-phase oscillator configured to output a first differential signal and a second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, the four-phase oscillator including

a first oscillator configured to output a first differential signal, the first oscillator including

a first resonator including an inductor and a capacitor coupled in parallel,

a first cross-coupled circuit in which a first pair of transistors coupled to the first resonator are cross-coupled,

a first tail current source coupled to the first pair of transistors,

first input differential pair transistors configured to receive a second differential signal, and

a second tail current source coupled to the first input differential pair transistors;

a second oscillator configured to output the second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, the second oscillator including

a second resonator including an inductor and a capacitor coupled in parallel,

a second cross-coupled circuit in which a second pair of transistors coupled to the second resonator are cross-coupled,

a third tail current source coupled to the second pair of transistors,

second input differential pair transistors configured to receive the first differential signal, and

a fourth tail current source coupled to the second input differential pair transistors, and

a control circuit configured to change the frequency of the first and second differential signals by controlling at least one of a difference between a first current value supplied from the first tail current source and a second current value supplied from the second tail current source and a difference between a third current value supplied from the third tail current source and a fourth current value supplied from the fourth tail current source;

an inverter configured to output a third differential signal inverted the phase of the second differential signal based on the change of the frequency by the control circuit;

a first phase detect circuit configured to output a first phase detect signal based on a difference between a received data signal and the first differential signal;

a second phase detect circuit configured to output a second phase detect signal based on a difference between a received data signal and the second differential signal;

a frequency detect circuit configured to compare the first phase detect signal with the second phase detect signal, and output a frequency detect signal based on a difference between the received signal and the first differential signal;

a control voltage generation circuit configured to generate a control voltage to adjust frequencies and phases of the first differential signal and the second differential signal based on the first phase detect signal and the frequency detect signal;

a data generation circuit configured to regenerate data from the received data according to the first differential signal.