Time-interleaved charge sampler receiver
A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.
1. A receiver comprising:
a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor;
a current buffer configured to drive the time-interleaved charge sampler; and
a dump switch coupled to the current buffer and in parallel with the charge sampler capacitor.
2. The receiver of claim 1 , in which the current buffer is differential and drives a first differential input path and a second differential input path of the time-interleaved charge sampler.
3. The receiver of claim 2 , further comprising a reset switch coupled between the first differential input path and the second differential input path of the time-interleaved charge sampler.
4. The receiver of claim 1 , integrated into a low-power 5G receiver.
5. The receiver of claim 1 , integrated into a current steering digital-to-analog converter of a low-power 5G transmitter.
6. The receiver of claim 1 , further comprising:
a differential low noise amplifier (LNA);
a mixer coupled in series with the differential LNA;
a current-mode filter coupled in series between the mixer and the current buffer, in which the differential LNA, the mixer, and the current-mode filter are integrated on a wireless transceiver (WTR) chip; and
an analog-to-digital converter (ADC) chip coupled to the WTR chip by a system-in-package (SIP) link, in which the current buffer and the time-interleaved charge sampler are integrated on the ADC chip.
7. The receiver of claim 1 , further comprising a plurality of the charge sampler switch in series with a plurality of the charge sampler capacitor for each phase of a clock pulse signal.
8. The receiver of claim 1 , in which the current buffer is directly coupled to the time-interleaved charge sampler.
9. The receiver of claim 1 , in which the current buffer comprises a first current buffer and a second current buffer according to even phases and odd phases of a clock pulse signal.
10. A method of using a time-interleaved charge sampler, comprising:
sampling a current-mode input signal at a charge sampler switch to integrate an analog value of the current-mode input signal in a charge sampler capacitor;
quantizing the analog value integrated in the charge sampler capacitor; and
controlling the charge sampler switch and a dump switch to attenuate the current-mode input signal at an aliasing frequency.
11. The method of claim 10 , further comprising:
generating clock phases to control the charge sampler switch and the dump switch; and
sampling edges of the clock phases to control the charge sampler switch and the dump switch, the edges aligned in time to attenuate the current-mode input signal at the aliasing frequency.
12. The method of claim 10 , further comprising extending an integration window with two current buffers to feed a first differential input path and a second differential input path of the time-interleaved charge sampler.
13. The method of claim 12 , in which extending the integration window changes a sampling rate and moves a notch frequency from a sampling frequency to half of the sampling frequency.
14. The method of claim 10 , further comprising shorting a first differential input path and a second differential input path of the time-interleaved charge sampler during a non-overlapping clock period.
15. A receiver comprising:
a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor;
means for driving the time-interleaved charge sampler; and
a dump switch coupled to the means for driving and in parallel with the charge sampler capacitor.
16. The receiver of claim 15 , further comprising a reset switch coupled between a first differential input path and a second differential input path of the time-interleaved charge sampler.
17. The receiver of claim 15 , further comprising:
a differential low noise amplifier (LNA);
a mixer coupled in series with the differential LNA;
a current-mode filter coupled in series between the mixer and the means for driving, in which the differential LNA, the mixer, and the current-mode filter are integrated on a wireless transceiver (WTR) chip; and
an analog-to-digital converter (ADC) chip coupled to the WTR chip by a system-in-package (SIP) link, in which the means for driving and the time-interleaved charge sampler are integrated on the ADC chip.
18. The receiver of claim 15 , in which the means for driving comprises a first driving means and a second driving means according to even phases and odd phases of a clock pulse signal.