Feed forward bias system for MTJ voltage control
The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.
1. A magnetic memory, comprising:
a first common line having a first end and a second end;
a second common line having a first end and a second end;
a memory cell that includes:
a select device having a first electrode and a second electrode, wherein the first electrode is connected to the first end of the first common line; and
a magnetic memory element coupled in series between the second electrode of the select device and the first end of the second common line;
a first voltage driver, wherein the first voltage driver is coupled to the second end of the second common line, and
a bias voltage generation circuit, wherein the bias voltage generation circuit is configured to provide a first bias voltage to the first voltage driver and includes a current reference device, wherein the current reference device includes a trimming device for controlling an amount of current flowing through the current reference device, and wherein the first voltage driver is configured to provide a first driving voltage to the second end of the second common line during an access operation.
2. The magnetic memory of claim 1 , wherein the magnetic memory element is a magnetic tunnel junction.
3. The magnetic memory of claim 1 , wherein the first common line is a source line.
4. The magnetic memory of claim 1 , wherein the second common line is a bit line.
5. The magnetic memory of claim 1 , wherein the bias voltage generation circuit includes a diode-connected NMOS device.
6. The magnetic memory of claim 1 , wherein the bias voltage generation circuit is configured to generate the first bias voltage by passing a current through a series of replica devices.
7. The magnetic memory of claim 1 , further comprising a second voltage driver, wherein the second voltage driver is coupled to the second end of the first common line.
8. The magnetic memory of claim 7 , wherein the second voltage driver is configured to provide a second driving voltage to the first end of the first common line during the access operation.
9. The magnetic memory of claim 8 , wherein the access operation includes one of a read and write operation.
10. A magnetic memory, comprising:
a first common line having a first end and a second end;
a second common line having a first end and a second end;
a memory cell that includes:
a select device having a first electrode and a second electrode, wherein the first electrode is connected to the first end of the first common line; and
a magnetic memory element coupled in series between the second electrode of the select device and the first end of the second common line;
a first voltage driver, wherein the first voltage driver is coupled to the second end of the second common line;
a second voltage driver, wherein the second voltage driver is coupled to the second end of the first common line;
a first bias voltage generation circuit; and
a second bias voltage generation circuit, wherein the first bias voltage generation circuit is configured to provide a first bias voltage to the first voltage driver during an access operation and includes a first current reference device, wherein the first current reference device includes a first trimming device for controlling an amount of current flowing through the first current reference device, and the second bias voltage generation circuit is configured to provide a second bias voltage to the second voltage driver during the access operation.
11. The magnetic memory of claim 10 , wherein the magnetic memory element is a magnetic tunnel junction.
12. The magnetic memory of claim 10 , wherein the first common line is a source line.
13. The magnetic memory of claim 10 , wherein the second common line is a bit line.
14. The magnetic memory of claim 10 , wherein the first bias voltage generation circuit includes a first diode-connected NMOS device.
15. The magnetic memory of claim 10 , wherein the first bias voltage generation circuit is configured to generate the first bias voltage by passing a current through a series of replica devices.
16. The magnetic memory of claim 10 , wherein the first voltage driver is configured to generate a first driving voltage based on the first bias voltage.
17. The magnetic memory of claim 10 , wherein the second voltage driver is configured to generate a second driving voltage based on the second bias voltage.
18. The magnetic memory of claim 10 , wherein the access operation includes one of a read and write operation.