IP Library Granted Patent US 10,658,233
Granted Patent B2
US 10,658,233 · App. 16/163,256 · Granted May 19, 2020

Dielectric damage-free dual damascene Cu interconnects without barrier at via bottom

Inventors: Koichi Motoyama (Clifton Park, NY); Benjamin D. Briggs (Waterford, NY); Gangadhara Raja Muthinti (Albany, NY); Cornelius Brown Peethala (Slingerlands, NY); Lawrence A. Clevenger (Saratoga Springs, NY)
Assignee: International Business Machines Corporation
H01L21/76844H01L21/76802H01L21/76862H01L21/76877H01L23/5226H01L23/53238
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Quick Facts
Patent No.
US 10,658,233
App. No.
16/163,256
Granted
May 19, 2020
Kind
B2
Abstract

Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.

Claims (17)

1. A method for forming a copper (Cu) interconnect structure, the method comprising the steps of:

forming a via and a trench in a dielectric over a metal line M1;

depositing a first barrier layer into, and lining, the via and the trench;

removing the first barrier layer from a bottom of the via and a bottom of the trench by selectively oxidizing portions of the first barrier layer along the bottom of the via and the bottom of the trench using neutral beam oxidation that does not damage the dielectric, and removing the portions of the first barrier layer that have been oxidized including at the bottom of the via such that the first barrier layer remains along only sidewalls of the via and the trench;

depositing Cu into the via in direct contact with the metal line M1 to form a via V1;

at least partially removing the first barrier layer that remains along the sidewalls of the trench;

lining the trench with a second barrier layer that covers a top of the via V1; and

depositing Cu into the trench over the second barrier layer to form a metal line M2.

2. The method of claim 1 , wherein the first barrier layer and the second barrier layer each comprises a material selected from the group consisting of: tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), titanium (Ti), tantalum (Ta) and combinations thereof.

3. The method of claim 2 , wherein the first barrier layer comprises a same material as the second barrier layer.

4. The method of claim 1 , wherein the Cu is deposited into the trench using an electroless Cu plating, the method further comprising the step of:

depositing a Cu seed layer onto the second barrier layer in the trench.

5. The method of claim 1 , wherein the dielectric comprises:

a capping layer on the metal line M1; and

an interlayer dielectric on the capping layer.

6. The method of claim 5 , wherein the capping layer comprises a material selected from the group consisting of: silicon carbon nitride (SiCN), hydrogen silicon carbon nitride (SiCNH), aluminum nitride (AlN) and combinations thereof.

7. The method of claim 5 , wherein the capping layer comprises an ultralow-κ dielectric having a dielectric constant κ of less than 2.7.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2018
From: MOTOYAMA, KOICHI; BRIGGS, BENJAMIN D.; MUTHINTI, GANGADHARA RAJA; PEETHALA, CORNELIUS BROWN; CLEVENGER, LAWRENCE A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 047202/0132 →
Continuity (1)
Related Publication 20200126854A1 · Apr 23, 2020
Cited By (1)
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