Integrated circuit substrate and method of making
According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.
1. A substrate for an integrated circuit, the substrate comprising:
a dielectric layer; and
a conductive layer extending in an x or y direction and at least partially embedded within the dielectric layer, the conductive layer comprising:
a via having a first end and an opposite second end, wherein the via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end, and the via has a non-tapered profile in the z-direction;
a capture pad attached to the via having a major diameter equivalent to a major diameter of the via; and
a trace adjacent to the via and having a second height in the z-direction that is different than the first height, wherein
the via has a constant width.
2. The substrate of claim 1 , wherein the dielectric layer comprises a dielectric material chosen from an epoxy laminate, polytetrafluoroethylene, phenolic cotton pater, woven glass, or mixtures thereof.
3. The substrate of claim 1 , wherein the conductive layer comprises copper.
4. The substrate of claim 1 , wherein the first height ranges from about 1.5 times to about 4 times greater than the second height.
5. The substrate of claim 1 , wherein a width of the via ranges from about 1.5 times to about 4 times greater than a width of the trace.