IP Library Granted Patent US 10,658,366
Granted Patent B2
US 10,658,366 · App. 15/920,468 · Granted May 19, 2020

Semiconductor device and method for fabricating the same

Inventors: Chia-Liang Liao (Yunlin County, TW); Feng-Yi Chang (Tainan, TW); Fu-Che Lee (Taichung, TW); Chieh-Te Chen (Kaohsiung, TW); Yi-Wang Zhan (Taichung, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L27/10855H01L21/31116H01L21/7687H01L21/76805H01L21/76816H01L21/76877H01L21/76895H01L23/5226H01L23/535H01L23/53257H01L23/53223H01L23/53238H01L23/53266H01L27/10814
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Quick Facts
Patent No.
US 10,658,366
App. No.
15/920,468
Granted
May 19, 2020
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.

Claims (31)

1. A method for fabricating semiconductor device, comprising:

providing a material layer having a contact pad therein;

forming a dielectric layer on the material layer and the contact pad;

forming a doped oxide layer on the dielectric layer;

forming an oxide layer on the doped oxide layer;

performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole;

performing a second etching process to remove part of the doped oxide layer to form a second contact hole after removing part of the dielectric layer and exposing the contact pad; and

forming a conductive layer in the second contact hole to form a contact plug.

2. The method of claim 1 , wherein the dielectric layer comprises silicon nitride.

3. The method of claim 1 , wherein the doped oxide layer comprises borosilicate phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

4. The method of claim 1 , wherein the oxide layer comprises tetraethyl orthosilicate (TEOS).

5. The method of claim 1 , wherein the second etching process uses a gas selected from the group consisting of ammonia (NH 3 ) and nitrogen trifluoride (NF 3 ).

6. The method of claim 1 , wherein an etching selectivity of the doped oxide layer to the oxide layer is 200:1.

7. The method of claim 1 , further comprising a first step portion between the doped oxide layer and the dielectric layer.

8. The method of claim 1 , further comprising a second step portion between the doped oxide layer and the oxide layer.

9. The method of claim 1 , wherein the contact plug comprises tungsten.

10. The method of claim 1 , wherein the contact plug comprises a first portion in the dielectric layer, a second portion in the doped oxide layer, and a third portion in the oxide layer.

11. The method of claim 10 , wherein the first portion comprises a first inclined sidewall, the second portion comprises a vertical sidewall, and the third portion comprises a second inclined sidewall.

12. The method of claim 10 , further comprising an air gap in the second portion.

13. A semiconductor device, comprising:

a contact pad in a material layer;

a dielectric layer on the material layer and the contact pad;

a doped oxide layer on the dielectric layer;

an oxide layer on the doped oxide layer; and

a contact plug comprising a first portion in the dielectric layer, a second portion in the doped oxide layer, and a third portion in the oxide layer, wherein the second portion comprises an air gap in the doped oxide layer and a top surface of the air gap is lower than a top surface of the doped oxide layer.

14. The semiconductor device of claim 13 , wherein the dielectric layer comprises silicon nitride.

15. The semiconductor device of claim 13 , wherein the doped oxide layer comprises borosilicate phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

16. The semiconductor device of claim 13 , wherein the oxide layer comprises tetraethyl orthosilicate (TEOS).

17. The semiconductor device of claim 13 , further comprising a first step portion between the doped oxide layer and the dielectric layer.

18. The semiconductor device of claim 13 , further comprising a second step portion between the doped oxide layer and the oxide layer.

19. The semiconductor device of claim 13 , wherein the first portion comprises a first inclined sidewall, the second portion comprises a vertical sidewall, and the third portion comprises a second inclined sidewall.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2018
From: LIAO, CHIA-LIANG; CHANG, FENG-YI; LEE, FU-CHE; CHEN, CHIEH-TE; ZHAN, YI-WANG
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 045215/0469 →
Priority Claims (1)
CN 2017 1 0292085 · Apr 28, 2017 · national
Continuity (1)
Related Publication 20180315759A1 · Nov 1, 2018