IP Library › Granted Patent US 10,658,369
Granted Patent B2
US 10,658,369 · App. 16/027,356 · Granted May 19, 2020

Semiconductor device and method for fabricating the same

Inventors: Kun-Hsin Chen (Pingtung County, TW); Hsuan-Tung Chu (Tainan, TW); Tsuo-Wen Lu (Kaohsiung, TW); Po-Chun Chen (Tainan, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L27/10894H01L21/0217H01L21/0228H01L21/02164H01L21/76229H01L27/10897H01L29/0649
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Quick Facts
Patent No.
US 10,658,369
App. No.
16/027,356
Granted
May 19, 2020
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner, wherein the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.

Claims (20)

1. A semiconductor device, comprising:

a substrate having a memory region and a periphery region;

a first isolation structure in the substrate on the memory region, wherein the first isolation comprises:

a first liner in the substrate; and

a second liner on the first liner;

a second isolation structure adjacent to the first isolation structure, wherein a width of the second isolation structure is greater than a width of the first isolation structure, the second isolation structure comprises:

the first liner in the substrate;

the second liner on the first liner; and

a third liner on the second liner of the second isolation structure and not on the second liner of the first isolation structure.

2. The semiconductor device of claim 1 , further comprising a third isolation structure and a fourth isolation structure in the substrate on the periphery region, wherein a width of the third isolation structure is greater than a width of the second isolation structure and a width of the fourth isolation structure is greater than a width of the third isolation structure.

3. The semiconductor device of claim 2 , wherein each of the third isolation structure and the fourth isolation structure comprises:

the first liner in the substrate;

the second liner on the first liner; and

the third liner on the second liner.

4. The semiconductor device of claim 3 , further comprising a fourth liner on the third liner.

5. The semiconductor device of claim 4 , wherein the third liner and the fourth liner comprise different materials.

6. The semiconductor device of claim 4 , wherein the third liner comprises silicon nitride and the fourth liner comprises silicon oxide.

7. The semiconductor device of claim 1 , wherein the first liner and the second liner comprise same material.

8. The semiconductor device of claim 7 , wherein the first liner and the second liner comprise silicon oxide.

9. The semiconductor device of claim 1 , wherein each of the first liner, the second liner, and the third liner is U-shaped.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 4, 2018
From: CHEN, KUN-HSIN; CHU, HSUAN-TUNG; LU, TSUO-WEN; CHEN, PO-CHUN
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 046266/0450 →
Priority Claims (1)
CN 2018 1 0586454 · Jun 8, 2018 · national
Continuity (1)
Related Publication 20190378844A1 · Dec 12, 2019