Method for manufacturing OLED backplane comprising active layer formed of first, second, and third oxide semiconductor layers

1. A method for manufacturing an organic light-emitting diode (OLED) backplane, comprising:

a step S 1 , comprising providing a base substrate, and forming a buffer layer on the base substrate;

a step S 2 , comprising depositing a first oxide semiconductor layer on the buffer layer, and introducing an argon gas and an oxygen gas with a flow ratio of the argon gas to the oxygen gas being a first ratio during the deposition of the first oxide semiconductor layer;

a step S 3 , comprising depositing a second oxide semiconductor layer on the first oxide semiconductor layer, and introducing the argon gas and the oxygen gas with a flow ratio of the argon gas to the oxygen gas being a second ratio during the deposition of the second oxide semiconductor layer;

a step S 4 , comprising depositing a third oxide semiconductor layer on the second oxide semiconductor layer, and introducing the argon gas and the oxygen gas with a flow ratio of the argon gas to the oxygen gas being a third ratio during the deposition of the third oxide semiconductor layer such that an active layer comprising the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer is obtained;

a step S 5 , comprising forming, over the active layer, a gate insulating layer and a gate electrode on the gate insulating layer;

a step S 6 , comprising covering the active layer, the gate electrode and the gate insulating layer with an interlayer insulating layer thereon; and

a step S 7 , comprising forming a source electrode and a drain electrode on the interlayer insulating layer,

wherein the first ratio and the third ratio are both greater than the second ratio, and the first ratio and the third ratio are both 4:1, and the second ratio is 20:1.

2. The method for manufacturing an OLED backplane as claimed in claim 1 , wherein a thickness of the first oxide semiconductor layer and the third oxide semiconductor layer is in a range from 50 Å to 100 Å, and a thickness of the second oxide semiconductor layer is in a range from 200 Å to 800 Å.

3. The method for manufacturing an OLED backplane as claimed in claim 1 , wherein the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer are both an indium gallium zinc oxide (IGZO) material, and wherein the buffer layer and the gate insulating layer are both one of or a combination of silicon oxide and silicon nitride.

4. The method for manufacturing an OLED backplane as claimed in claim 1 , wherein the step S 1 further comprises:

forming a light shielding layer between the base substrate and the buffer layer, wherein the light shielding layer shields the active layer.

5. The method for manufacturing an OLED backplane as claimed in claim 1 , wherein the step S 5 specifically comprises:

depositing a gate insulating film on the active layer and the buffer layer, and depositing a gate metal film on the gate insulating film;

patterning the gate metal film by a mask process to form the gate electrode; and

etching the gate insulating film with the gate electrode as a mask to form the gate insulating layer.

6. The method for manufacturing an OLED backplane as claimed in claim 1 , wherein in the step S 5 , the gate electrode and the gate insulating layer cover a center of the active layer and expose two ends of the active layer,

wherein between the step S 5 and the step S 6 , the method further comprises:

performing a plasma treatment on the active layer such that a resistance of the two ends of the active layer is reduced to form an N+ conductor layer.

7. The method for manufacturing an OLED backplane as claimed in claim 1 , wherein the step S 6 further comprises:

patterning the interlayer insulating layer to form a first via hole and a second via hole respectively exposing the two ends of the active layer, wherein in the step S 7 , the source electrode and the drain electrode are respectively in contact with the two ends of the active layer through the first via hole and the second via hole.

8. The method for manufacturing an OLED backplane as claimed in claim 1 , further comprising:

a step S 8 , comprising depositing a passivation layer on the interlayer insulating layer, the source electrode and the drain electrode, and patterning the passivation layer to form a third via hole exposing the drain electrode;

a step S 9 , comprising forming a first electrode on the passivation layer, wherein the first electrode is in contact with the drain electrode through the third via hole;

a step S 10 , comprising forming a pixel defining layer on the first electrode and the passivation layer, and patterning the pixel defining layer to form a pixel defining recess exposing the first electrode; and

a step S 11 , comprising forming an organic light-emitting layer in the pixel defining recess, and forming a second electrode on the pixel defining layer and the organic light-emitting layer.

9. The method for manufacturing an OLED backplane as claimed in claim 8 , wherein the first electrode is a transparent electrode, and the second electrode is a reflective electrode.

10. A method for manufacturing an OLED backplane, comprising:

a step S 1 , comprising providing a base substrate, and forming a buffer layer on the base substrate;

a step S 2 , comprising depositing a first oxide semiconductor layer on the buffer layer, and introducing an argon gas and an oxygen gas with a flow ratio of the argon gas to the oxygen gas being a first ratio during the deposition of the first oxide semiconductor layer;

a step S 3 , comprising depositing a second oxide semiconductor layer on the first oxide semiconductor layer, and introducing the argon gas and the oxygen gas with a flow ratio of the argon gas to the oxygen gas being a second ratio during the deposition of the second oxide semiconductor layer;

a step S 4 , comprising depositing a third oxide semiconductor layer on the second oxide semiconductor layer, and introducing the argon gas and the oxygen gas with a flow ratio of the argon gas to the oxygen gas being a third ratio during the deposition of the third oxide semiconductor layer such that an active layer comprising the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer is obtained;

a step S 5 , comprising forming, over the active layer, a gate insulating layer and a gate electrode on the gate insulating layer;

a step S 6 , comprising covering the active layer, the gate electrode and the gate insulating layer with an interlayer insulating layer thereon; and

a step S 7 , comprising forming a source electrode and a drain electrode on the interlayer insulating layer,

wherein the first ratio and the third ratio are both greater than the second ratio,

wherein the first ratio and the third ratio are both 4:1, and the second ratio is 20:1,

wherein a thickness of the first oxide semiconductor layer and the third oxide semiconductor layer is in a range from 50 Å to 100 Å, and a thickness of the second oxide semiconductor layer is in a range from 200 Å to 800 Å,

wherein the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer are both an IGZO material, and the buffer layer and the gate insulating layer are both one of or a combination of silicon oxide and silicon nitride,

wherein the step S 1 further comprises:

forming a light shielding layer between the base substrate and the buffer layer, wherein the light shielding layer shields the active layer,

wherein the step S 5 specifically comprises:

depositing a gate insulating film on the active layer and the buffer layer, and depositing a gate metal film on the gate insulating film;

patterning the gate metal film by a mask process to form the gate electrode; and

etching the gate insulating film with the gate electrode as a mask to form the gate insulating layer.

11. The method for manufacturing an OLED backplane as claimed in claim 10 , wherein in the step S 5 , the gate electrode and the gate insulating layer cover a center of the active layer and expose two ends of the active layer,

Wherein between the step S 5 and the step S 6 , the method further comprises:

performing a plasma treatment on the active layer such that a resistance of the two ends of the active layer is reduced to form an N+ conductor layer.

12. The method for manufacturing an OLED backplane as claimed in claim 10 , wherein the step S 6 further comprises:

patterning the interlayer insulating layer to form a first via hole and a second via hole respectively exposing the two ends of the active layer, wherein in the step S 7 , the source electrode and the drain electrode are respectively in contact with the two ends of the active layer through the first via hole and the second via hole.

13. The method for manufacturing an OLED backplane as claimed in claim 10 , further comprising:

a step S 8 , comprising depositing a passivation layer on the interlayer insulating layer, the source electrode and the drain electrode, and patterning the passivation layer to form a third via hole exposing the drain electrode;

a step S 9 , comprising forming a first electrode on the passivation layer, wherein the first electrode is in contact with the drain electrode through the third via hole;

a step S 10 , comprising forming a pixel defining layer on the first electrode and the passivation layer, and patterning the pixel defining layer to form a pixel defining recess exposing the first electrode; and

a step S 11 , comprising forming an organic light-emitting layer in the pixel defining recess, and forming a second electrode on the pixel defining layer and the organic light-emitting layer.

14. The method for manufacturing an OLED backplane as claimed in claim 13 , wherein the first electrode is a transparent electrode, and the second electrode is a reflective electrode.