IP Library › Granted Patent US 10,658,470
Granted Patent B2
US 10,658,470 · App. 15/959,411 · Granted May 19, 2020

Device with doped phosphorene and method for doping phosphorene

Inventors: Yu-Ming Lin (Hsinchu, TW); Chao-Hsin Wu (Taipei, TW); Hsun-Ming Chang (Kaohsiung, TW); Samuel C. Pan (Hsinchu, TW)
Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.; NATIONAL TAIWAN UNIVERSITY
H01L29/24H01L21/385H01L29/0649H01L29/1033H01L29/267H01L29/401H01L29/45H01L29/66969H01L29/778H01L29/7786H01L29/786H01L29/78696H01L29/861H01L21/47573H01L29/66545H01L29/66742
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Quick Facts
Patent No.
US 10,658,470
App. No.
15/959,411
Granted
May 19, 2020
Kind
B2
Abstract

A method includes providing a black phosphorus (BP) layer over a substrate, forming a dopant source layer over the BP layer, annealing the dopant source layer to drive a dopant from the dopant source layer into the BP layer, and forming a conductive contact over the dopant source layer.

Claims (42)

1. A method, comprising:

providing a black phosphorus (BP) layer over a substrate;

forming a dopant source layer over a source/drain region of the BP layer, wherein a channel region of the BP layer is free from coverage by the dopant source layer;

annealing the dopant source layer to drive a dopant from the dopant source layer into the BP layer; and

forming a conductive contact over the dopant source layer.

2. The method of claim 1 , wherein annealing the dopant source layer is performed such that the BP layer is metallized.

3. The method of claim 1 , wherein annealing the dopant source layer is performed such that phosphorus in the BP layer is transformed into a phosphide.

4. The method of claim 1 , further comprising forming a dielectric layer over the substrate prior to providing the BP layer.

5. The method of claim 4 , wherein the substrate comprises doped silicon.

6. The method of claim 1 , further comprising:

forming a cap metal layer over the dopant source layer prior to annealing the dopant source layer.

7. The method of claim 1 , further comprising:

forming a noble metal layer over the dopant source layer prior to forming the conductive contact.

8. The method of claim 7 , wherein forming the conductive contact is performed such that the conductive contact is formed over the noble metal layer.

9. The method of claim 1 , wherein the dopant in the dopant source layer comprises an element of Group III, an element of Group IV, or an element of Group VI.

10. The method of claim 1 , wherein forming the dopant source layer comprises forming a blanket dopant source layer over the BP layer, and patterning the blanket dopant source layer to expose the channel region of the BP layer.

11. A method, comprising:

providing a phosphorene-containing layer over a substrate;

forming a gate stack over a channel region of the phosphorene-containing layer;

converting phosphorene in a source/drain region of the phosphorene-containing layer into a compound of phosphorus and an element of Group III, IV, or VI; and

forming a source/drain contact over the source/drain region.

12. The method of claim 11 , further comprising:

replacing a dummy gate electrode of the gate stack with a metal gate electrode after converting the phosphorene into the compound.

13. The method of claim 11 , further comprising:

forming a gate spacer on a sidewall of the gate stack prior to converting the phosphorene into the compound.

14. The method of claim 11 , wherein converting the phosphorene into the compound comprises:

forming a dopant source layer over the source/drain region, the dopant source layer comprising a dopant having the element of Group III, IV or VI; and

elevating temperatures of the dopant source layer and the phosphorene-containing layer to react the dopant with the phosphorene-containing layer.

15. The method of claim 14 , wherein elevating the temperatures of the dopant source layer and the phosphorene-containing layer is performed such that the channel region of the phosphorene-containing layer is substantially free from reacting with the dopant.

16. The method of claim 11 , further comprising:

forming a two-dimensional insulator layer over the phosphorene-containing layer prior to forming the gate stack; and

removing a first portion of the two-dimensional insulator layer from the source/drain region, wherein a second portion of the two-dimensional insulator layer remains on the channel region.

17. A method, comprising:

providing a black phosphorus (BP) layer over a substrate;

metallizing source/drain regions of the BP layer, wherein a channel region of the BP layer between the source/drain regions of the BP layer remains semiconductive after metallizing the source/drain regions; and

forming source/drain contacts respectively over the metallized source/drain regions of the BP layer.

18. The method of claim 17 , wherein metallizing the source/drain regions comprises:

forming a germanium-containing layer over the source/drain regions; and

diffusing germanium from the germanium-containing layer into the source/drain regions.

19. The method of claim 18 , wherein diffusing the germanium from the germanium-containing layer into the source/drain regions is performed using an anneal process.

20. The method of claim 17 , further comprising:

forming a noble metal material over the source/drain regions prior to metallizing the source/drain regions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2018
From: LIN, YU-MING; WU, CHAO-HSIN; CHANG, HSUN-MING; PAN, SAMUEL C.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.; NATIONAL TAIWAN UNIVERSITY
Reel/Frame 045615/0681 →
Continuity (2)
Provisional Application 62586097 · Nov 14, 2017
Related Publication 20190148499A1 · May 16, 2019