Semiconductor device and manufacturing method thereof
A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.
1. A semiconductor device comprising:
a plurality of fin structures extending in a first direction disposed on a semiconductor substrate, wherein a lower portion of the fin structures is embedded in a first insulating layer;
a first gate electrode structure and a second gate electrode structure extending in a second direction substantially perpendicular to the first direction disposed over the plurality of fin structures and the first insulating layer, wherein the first gate electrode structure and second gate electrode structure are spaced apart from each other and extend along a line in a same direction;
first and second insulating sidewall spacers arranged on opposing side surfaces of the first and second gate electrode structures, wherein each of the first and second insulating sidewall spacers contiguously extend along the second direction;
a second insulating layer disposed in a region between the first gate electrode structure and second gate electrode structure, wherein the second insulating layer separates the first gate electrode structure from the second gate electrode structure; and
a third insulating layer disposed in the region between the first gate electrode structure and the second gate electrode structure, wherein the third insulating layer is formed of a different material than the second insulating layer.
2. The semiconductor device of claim 1 , wherein the second insulating layer is formed of a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and SiCON.
3. The semiconductor device of claim 1 , wherein the second insulating layer has a thickness of 5 Å to 200 Å.
4. The semiconductor device of claim 1 , wherein the third insulating layer is formed of a material selected from the group consisting of silicon dioxide, silicon oxynitride, silicon carbide, silicon oxycarbide, and SiCON.
5. The semiconductor device of claim 1 , wherein the third insulating layer has a thickness of 5 Å to 200 Å.
6. The semiconductor device of claim 1 , wherein the third insulating layer is disposed on opposing sidewalls of the first gate electrode structure and the second gate electrode structure.
7. A semiconductor device comprising:
a plurality of fin structures extending in a first direction disposed on a semiconductor substrate;
a first gate electrode structure and a second gate electrode structure extending in a second direction substantially perpendicular to the first direction disposed over the plurality of fin structures, wherein the first gate electrode structure and second gate electrode structure are spaced apart from each other and extend along a line in a same direction;
first and second insulating sidewall spacers arranged on opposing side surfaces of the first and second gate electrode structures;
a first insulating layer disposed in a region between the first gate electrode structure and the second gate electrode structure;
a second insulating layer disposed in the region between the first gate electrode structure and second gate electrode structure, wherein a length H 2 of the second insulating layer between the first gate electrode structure and the second gate electrode structure is greater at an interior portion of the second insulating layer than a length H 1 of the second insulating layer between the first gate electrode structure and the second gate electrode structure at an edge portion of the second insulating layer in plan view.
8. The semiconductor device of claim 7 , wherein the second insulating layer is formed of a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and SiCON.
9. The semiconductor device of claim 7 , wherein the lengths of H 1 and H 2 range from 1 nm to 200 nm.
10. The semiconductor device of claim 7 , wherein the first insulating layer and the second insulating layer are formed of different materials.
11. The semiconductor device of claim 10 , wherein the first insulating layer is formed of a material selected from the group consisting of silicon dioxide, silicon oxynitride, silicon carbide, silicon oxycarbide, and SiCON.
12. The semiconductor device of claim 7 , wherein the first insulating layer extends into the first and second insulating sidewall spacers as seen in plan view.
13. The semiconductor device of claim 7 , wherein the first and second insulating sidewall spacers are formed of a different material than the second insulating layer.
14. The semiconductor device of claim 7 , wherein the first and second insulating sidewall spacers are formed of a material selected from the group consisting of silicon carbide, silicon oxycarbide, and SiCON.
15. A semiconductor device comprising:
a plurality of fin structures extending in a first direction disposed on a semiconductor substrate;
a first gate electrode structure and a second gate electrode structure extending in a second direction substantially perpendicular to the first direction disposed over the plurality of fin structures, wherein the first gate electrode structure and second gate electrode structure are spaced apart from each other and extend along a line in a same direction;
first and second insulating sidewall spacers arranged on opposing side surfaces of the first and second gate electrode structures, wherein each of the first and second insulating sidewall spacers contiguously extend along the second direction;
a first insulating layer disposed in a region between the first gate electrode structure and second gate electrode structure, wherein the first insulating layer separates the first gate electrode structure from the second gate electrode structure; and
a second insulating layer in the region between the first gate electrode structure and the second gate electrode structure, wherein the first insulating layer surrounds the second insulating layer as seen in plan view.
16. The semiconductor device of claim 15 , wherein a thickness H 3 of the first insulating layer between the second insulating layer and the first gate electrode structure ranges from 0.5 nm to 50 nm.
17. The semiconductor device of claim 15 , wherein the first insulating layer extends into the first and second insulating sidewall spacers as seen in plan view.
18. The semiconductor device of claim 15 , wherein the first insulating layer and the second insulating layer are formed of different materials.
19. The semiconductor device of claim 15 , wherein the first and second insulating sidewall spacers are formed of a different material than the second insulating layer.
20. The semiconductor device of claim 15 , wherein the second insulating layer is formed of a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and SiCON.