A/D conversion device, gray code generation device, signal processing device, imaging element, and electronic device

1. A gray code generation device, comprising:

first circuitry configured to generate a delayed input clock signal based on a first delay in an input clock signal;

a first plurality of phase interpolators configured to generate a plurality of multi-phase clock signals with a second delay, based on the input clock signal and the delayed input clock signal, wherein

each of the generated plurality of multi-phase clock signals has a phase shift with respect to the input clock signal, and

the second delay is based on a phase difference between the input clock signal and the delayed input clock signal; and

second circuitry that includes a second plurality of phase interpolators and logic gates, wherein the second circuitry is configured to generate gray codes from the plurality of multi-phase clock signals.

2. The gray code generation device according to claim 1 , wherein

the second circuitry is further configured to:

generate a high-order gray code from a first multi-phase clock signal of the plurality of multi-phase clock signals; and

generate a low-order gray code from remaining multi-phase clock signals of the plurality of multiphase clock signals.

3. An analog to digital (A/D) conversion device, comprising:

first circuitry configured to generate a delayed input clock signal based on a first delay in an input clock signal;

a first plurality of phase interpolators configured to generate a plurality of multi-phase clock signals with a second delay, based on the input clock signal and the delayed input clock signal, wherein

each of the generated plurality of multi-phase clock signals has a phase shift with respect to the input clock signal, and

the second delay is based on a phase difference between the input clock signal and the delayed input clock signal;

second circuitry that includes a second plurality of phase interpolators and logic gates, wherein the second circuitry is configured to generate gray codes from the plurality of multi-phase clock signals; and

third circuitry configured to convert an input analog signal to obtain digital values based on the generated gray codes.

4. The A/D conversion device according to claim 3 , wherein the third circuitry is further configured to:

compare a reference voltage of a ramp waveform and an input voltage;

latch the generated gray codes using an inversion of an output of the comparison,

convert the generated gray codes into binary values; and

output the obtained digital values.

5. The A/D conversion device according to claim 4 , wherein the third circuitry is further configured to:

count a number of periods of the input clock signal; and

output, based on the count of the number of periods, a count value as a high order bit, wherein the obtained digital values are output as lower order bits.

6. An imaging element, comprising:

a pixel array including a plurality of unit pixels, wherein each unit pixel of the plurality of unit pixels includes a photoelectric conversion element configured to photoelectrically convert incident light;

first circuitry configured to generate a delayed input clock signal based on a first delay in an input clock signal;

a first plurality of phase interpolators configured to generate a plurality of multi-phase clock signals with a second delay, based on the input clock signal and the delayed input clock signal, wherein

each of the generated plurality of multi-phase clock signals has a phase shift with respect to the input clock signal, and

the second delay is based on a phase difference between the input clock signal and the delayed input clock signal;

second circuitry that includes a second plurality of phase interpolators and logic gates, wherein the second circuitry is configured to generate gray codes from the plurality of multi-phase clock signals; and

third circuitry configured to convert a first analog signal output from a first unit pixel of the plurality of unit pixels based on the generated gray codes.

7. The imaging element according to claim 6 , wherein

one of each column of the plurality of unit pixels or a partial region of the plurality of unit pixels includes the third circuitry,

the third circuitry is further configured to convert a second analog signal, output from a second unit pixel of a column of the plurality of unit pixels or the partial region, to a digital output signal, and

the conversion of the second analog signal to the digital output signal is based on the generated gray codes.

8. The imaging element according to claim 6 , wherein

one of a specific number of columns of the plurality of unit pixels or a specific number of partial regions of the plurality of unit pixels includes the second circuitry, and

the third circuitry is further configured to convert a second analog signal based on the gray codes generated by the second circuitry corresponding to one of the specific number of columns of the plurality of unit pixels or the specific number of partial regions of the plurality of unit pixels.

9. An electronic device, comprising:

an imaging sensor configured to image a subject to obtain image data; and

first circuitry configured to process the image data obtained by the imaging sensor,

wherein the imaging sensor includes:

a pixel array including a plurality of unit pixels, wherein each unit pixel of the plurality of unit pixels includes a photoelectric conversion element configured to photoelectrically converting incident light;

second circuitry configured to generate a delayed input clock signal based on a first delay in an input clock signal;

a first plurality of phase interpolators configured to generate a plurality of multi-phase clock signals with a second delay, based on the input clock signal and the delayed input clock signal, wherein

each of the generated plurality of multi-phase clock signals has a phase shift with respect to the input clock signal, and

the second delay is based on a phase difference between the input clock signal and the delayed input clock signal;

third circuitry that includes a second plurality of phase interpolators and logic gates, wherein the third circuitry is configured to generate gray codes from the plurality of multi-phase clock signals; and

fourth circuitry configured to convert an input analog signal output from an unit pixel of the pixel array based on the generated gray codes.