Differential physical layer device with testing capability
A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.
1. A circuit, comprising:
a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and
switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating a transmitter on another side of the link during the second mode, wherein each receiver comprises first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage.
2. The circuit of claim 1 , wherein each of the inputs and outputs comprises a differential pair of signals.
3. The circuit of claim 2 , wherein the receiver comprises a MIPI differential physical (D-PHY) receiver.
4. The circuit of claim 2 , wherein the receiver comprises a current source connected to drain terminals of first and second positive input transistors and first and second negative input transistors, and a first resistor connected to source terminals of the first and second positive input transistors, and a second resistor connected to source terminals of the first and second negative input transistors.
5. The circuit of claim 1 , wherein the second mode comprises a loop-back test mode.
6. The circuit of claim 1 , wherein the first mode comprises a receiver mode where the outputs track the first inputs.
7. The circuit of claim 1 , wherein the switches connect a resistor between either the first or second input ports.
8. A MIPI differential physical (D-PHY) system, comprising:
control and interface logic coupled to clock, data, control and test signals; transmitter and receiver clock circuits coupled to the control and interface logic;
a single data transmitter coupled to the control and interface logic; and
one or more data receivers coupled to control and interface logic and the single data transmitter, the one or more data receivers having a loop-back mode coupled to the single data transmitter for sequentially performing self-test on each data receiver, wherein each receiver comprises first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on another side of the link during the second mode.
9. The system of claim 8 , wherein each of the inputs and outputs comprises a differential pair of signals.
10. The system of claim 8 , wherein a second mode comprises a loop-back test mode.
11. The system of claim 8 , wherein a first mode comprises a receiver mode where differential outputs track the first differential inputs.
12. The system of claim 8 , wherein switches connect a resistor between either the first or second differential input ports.
13. A MIPI differential physical (D-PHY) system, comprising:
control and interface logic coupled to clock, data, control and test signals; transmitter and receiver clock circuits coupled to the control and interface logic;
a single data transmitter coupled to the control and interface logic; and
one or more data receivers coupled to control and interface logic and the single data transmitter, the one or more data receivers having a loop-back mode coupled to the single data transmitter for sequentially performing self-test on each data receiver, wherein the receiver comprises a current source connected to source terminals of first and second positive input transistors and first and second negative input transistors, and a first resistor connected to drain terminals of the first and second positive input transistors, and a second resistor connected to drain terminals of the first and second negative input transistors.