Electromagnetic shielding metal-insulator-metal capacitor structure
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.
1. A method of forming a semiconductor structure, the method comprising:
providing a substrate;
forming a first conducting line in a first metallization layer on the substrate;
depositing a first dielectric layer on the first metallization layer;
forming a metal-insulator-metal (MIM) capacitor in the first dielectric layer and over the first conducting line, wherein the forming the MIM capacitor comprises:
depositing first and second capacitor electrodes in the first dielectric layer and above the first conducting line;
depositing a second dielectric layer between the first and second capacitor electrodes;
electrically coupling the first and second capacitor electrodes to a ground voltage level; and
forming a second conducting line on the first dielectric layer and in a second metallization layer.
2. The method of claim 1 , wherein depositing the first and second capacitor electrodes comprises depositing the first capacitor electrode prior to depositing the second capacitor electrode.
3. The method of claim 1 , further comprising electrically connecting the second conducting line to a signal carrying line.
4. The method of claim 1 , wherein the first and second metallization layers are respectively M1 and M2 metallization layers of the semiconductor structure.
5. The method of claim 1 , wherein the second conducting line is formed directly above the first and second capacitor electrodes.
6. A method of forming a semiconductor interposer device, the method comprising:
forming a first conducting line in a first metallization layer;
depositing a first dielectric layer on the first metallization layer;
forming a bottom capacitor electrode of a metal-insulator-metal (MIM) capacitor in the first dielectric layer and above the first conducting line;
depositing a second dielectric layer on the bottom capacitor electrode;
forming a top capacitor electrode in the first dielectric layer;
electrically coupling the top capacitor electrode to a ground voltage level;
forming second and third conducting lines in a second metallization layer, wherein the second conducting line is electrically coupled to the ground voltage level; and
electrically coupling the bottom capacitor electrode to the second conducting line.
7. The method of claim 6 , further comprising electrically coupling the first conducting line to a signal carrying line.
8. The method of claim 6 , wherein the bottom capacitor electrode is formed directly over the first conducting line.
9. The method of claim 6 , further comprising electrically coupling the third conducting line to a signal carrying line.
10. The method of claim 9 , wherein the third conducting line is formed directly above the top capacitor electrode.
11. The method of claim 6 , wherein depositing the first and second dielectric layers comprise depositing low-k and high-k dielectric materials, respectively.
12. The method of claim 6 , further comprising:
forming a fourth conducting line in the second metallization layer; and
electrically coupling the fourth conducting line to the ground voltage level.
13. The method of claim 12 , further comprising electrically coupling the fourth conducting line to the top capacitor electrode.
14. The method of claim 6 , wherein the first metallization layer comprises an M1 metallization layer.
15. The method of claim 6 , wherein the second metallization layer comprises an M2 metallization layer.
16. A method of forming a semiconductor interposer device, the method comprising:
forming a first metallization layer above a substrate;
forming a first signal conducting line in the first metallization layer;
depositing a first dielectric layer on the first metallization layer;
forming a metal-insulator-metal (MIM) capacitor in the first dielectric layer and above the first signal conducting line, wherein forming the MIM capacitor comprises:
forming a bottom capacitor electrode in the first dielectric layer;
depositing a second dielectric layer on the bottom capacitor electrode; and
depositing a top capacitor electrode on the second dielectric layer;
forming a second metallization layer above the MIM capacitor;
forming a second signal line in the second metallization layer;
forming first and second ground voltage supply lines in the second metallization layer; and
electrically coupling the top and bottom capacitor electrodes to the first and second ground voltage supply lines, respectively.
17. The method of claim 16 , wherein the first signal conducting line comprises a signal carrying line configured to emit electromagnetic signals.
18. The method of claim 16 , wherein depositing the first and second dielectric layers comprise depositing low-k and high-k dielectric materials, respectively.
19. The method of claim 16 , wherein forming the second signal line comprises depositing a conductive material over the MIM capacitor.
20. The method of claim 16 , wherein the first and second metallization layers are M1 and M2 metallization layers, respectively.