Semiconductor structure and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a resistive random access memory cell, and a semiconductor element. The resistive random access memory cell is on the substrate. The resistive random access memory cell includes a first electrode having a U shape. The semiconductor element is adjoined with an outer sidewall of the first electrode.
1. A semiconductor structure, comprising:
a substrate;
a resistive random access memory cell on the substrate, and the resistive random access memory cell comprising a first electrode having a U shape, a second electrode and a resistive layer between the first electrode and the second electrode; and
a semiconductor element adjoined with an outer sidewall of the first electrode, wherein a top surface of the semiconductor element is coplanar with a top surface of the first electrode, and the semiconductor element is in direct contact with the resistive random access memory cell.
2. The semiconductor structure according to claim 1 , wherein the resistive layer has a U shape.
3. The semiconductor structure according to claim 1 , wherein the semiconductor element functions as a resistor.
4. The semiconductor structure according to claim 1 , further comprising opposing spacers respectively on the first electrode and the semiconductor element.
5. The semiconductor structure according to claim 1 , wherein the semiconductor element is a diode having a N-type portion and a P-type portion, one of the N-type portion and the P-type portion is adjoined with the outer sidewall of the first electrode.
6. The semiconductor structure according to claim 5 , wherein a PN junction between the N-type portion and the P-type portion is substantially parallel to the outer sidewall of the first electrode.
7. The semiconductor structure according to claim 1 , further comprising a transistor on the substrate and comprising a gate electrode, wherein the second electrode has a polarity opposing to a polarity of the first electrode, each of the gate electrode and the second electrode comprises an electrode film and an electrode layer on the electrode film having a U shape.
8. The semiconductor structure according to claim 1 , further comprising an isolation element, wherein the resistive random access memory cell and the semiconductor element are isolated from the substrate by the isolation element.
9. The semiconductor structure according to claim 1 , further comprising a transistor and a conductive element, wherein the transistor comprises a source/drain doped region in the substrate, the conductive element has a first lower surface and a second lower surface respectively electrically connected to the source/drain doped region and the semiconductor element.