Semiconductor device having channel regions
A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.
1. A method of manufacturing a semiconductor device, the method comprising:
stacking semiconductor layers on a substrate;
removing portions of the semiconductor layers and the substrate to form fin structures, the fin structures including protruding portions of the substrate and remaining portions of the semiconductor layers stacked on the protruding portions;
removing portions of the fin structures to form nanowires from the remaining portions of the semiconductor layers, the nanowires being separated from each other;
forming source/drain regions between and in contact with the nanowires, wherein first voids are formed between the source/drain regions and the substrate; and
forming gate electrodes surrounding the nanowires.
2. The method of claim 1 , wherein the stacking semiconductor layers on the substrate comprises alternately stacking the semiconductor layers and sacrificial layers on the substrate, and
wherein the method further comprises, after the removing the portions of the fin structures, removing portions of the sacrificial layers in regions from which the fin structures have been removed to form side spaces and filling the side spaces with an insulating material to form inner spacers between the nanowires and between a lowermost nanowire among the nanowires and the substrate.
3. The method of claim 2 , wherein, in a cross section taken in a first direction in which the protruding portions are extended, the first voids are sealed by the source/drain regions, the protruding portions, and lowermost inner spacers of the inner spacers.
4. The method of claim 1 , wherein a lower surface of each of the source/drain regions is lower than a lower surface of each of lowermost nanowires among of the nanowires.
5. The method of claim 1 , further comprising forming an isolation insulating layer on the substrate, the isolation insulating layer covering a portion of a side surface of the protruding portions.