Semiconductor circuit and semiconductor system
A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.
1. A semiconductor circuit comprising:
a clocked comparator configured to,
receive a first input signal and a second input signal from a host and
compare the first input signal and the second input signal; and
an offset application circuit configured to apply an offset to the first input signal,
wherein the clocked comparator is configured to be driven based on a reference clock provided from the host, and
wherein the second input signal is a wake-up signal.
2. The semiconductor circuit of claim 1 , wherein the clocked comparator is configured to,
power off when the provision of the reference clock from the host is stopped, and
power on when the provision of the reference clock from the host is resumed.
3. The semiconductor circuit of claim 1 , wherein the clocked comparator is configured to,
output a hibernation exit signal based on a result of comparing the first input signal and the second input signal, and
provide the hibernation exit signal to a power management unit (PMU).
4. The semiconductor circuit of claim 1 , wherein the second input signal transits from a DIF_Z value to a DIF_N value.
5. The semiconductor circuit of claim 1 , wherein the clocked comparator is configured to receive the first input signal and the second input signal from the host through a Mobile Industry Processor Interface (MIPI) M-PHY layer of a Universal Flash Storage (UFS) interface.
6. The semiconductor circuit of claim 1 , wherein the offset application circuit includes a plurality of differential input transistor circuits.
7. The semiconductor circuit of claim 6 , wherein the differential input transistor circuits includes,
a plurality of first differential input transistor circuits, each including a first transistor gated by a first enable signal and a second transistor gated by the first input signal and connected in series to the first transistor, and
a plurality of second differential input transistor circuits, each including a third transistor gated by a second enable signal and a fourth transistor gated by the second input signal and connected in series to the third transistor.
8. The semiconductor circuit of claim 7 , wherein the first enable signal of each of the plurality of the first differential input transistor circuits included in a portion of the plurality of the first differential input transistor circuits corresponds to a first logic value, and the first enable signal of each of the plurality of first differential input transistor circuits included in another portion of the plurality of the first differential input transistor circuits corresponds to a second logic value different from the first logic value.
9. The semiconductor circuit of claim 7 , wherein the second enable signal of each of the plurality of the second differential input transistor circuits included in a portion of the plurality of the second differential input transistor circuits corresponds to a first logic value, and the second enable signal of each of the plurality of the second differential input transistor circuits included in another portion of the plurality of the second differential input transistor circuits corresponds to a second logic value different from the first logic value.
10. The semiconductor circuit of claim 1 , further comprising:
a low pass filter configured to,
receive the first input signal and the second input signal from the host,
perform a low pass filter operation on the first input signal and the second input signal, and then
provide the first input signal and the second input signal to the clocked comparator.
11. The semiconductor circuit of claim 1 , further comprising:
a replica clocked comparator configured to,
be driven by the reference clock provided from the host and receives, and
compare an output signal of a replica offset application circuit and a reference voltage signal.
12. A semiconductor circuit comprising:
a clocked comparator configured to compare a first input signal and a second input signal received from a host through a Universal Flash Storage InterConnect layer (UIC);
an offset application circuit configured to apply an offset to the first input signal; and
a device controller electrically connected to the UIC,
wherein the clocked comparator is configured to,
be driven by a reference clock provided from the host when the device controller is not in a hibernation mode, and
not be driven by the reference clock after the device controller enters the hibernation mode, and
the clock comparator is configured to resume being driven by the reference clock before the device controller exits the hibernation mode.
13. The semiconductor circuit of claim 12 , wherein the clocked comparator is configured to,
power off when the provision of the reference clock from the host is stopped, and
power on when the provision of the reference clock from the host is resumed.
14. The semiconductor circuit of claim 12 , wherein the clocked comparator is configured to,
output a hibernation exit signal based on a result of comparing the first input signal and the second input signal, and
provide the hibernation exit signal to a power management unit (PMU), and the PMU provides power to the device controller.
15. The semiconductor circuit of claim 12 , wherein the second input signal is a wake-up related signal and transits from a DIF_Z value to a DIF_N value.
16. The semiconductor circuit of claim 12 , wherein the clocked comparator is configured to receive the first input signal and the second input signal from the host through a MIPI M-PHY layer of a UFS interface.
17. A semiconductor circuit comprising:
a clocked comparator configured to,
receive a first input signal and a second input signal from a host and
compare the first input signal and the second input signal; and
an offset application circuit configured to apply an offset to the first input signal,
wherein the clocked comparator is configured to be driven based on a reference clock provided from the host, and
wherein the offset application circuit includes a plurality of differential input transistor circuits.
18. The semiconductor circuit of claim 17 , wherein the clocked comparator is configured to,
power off when the provision of the reference clock from the host is stopped, and
power on when the provision of the reference clock from the host is resumed.
19. The semiconductor circuit of claim 17 , wherein the clocked comparator is configured to,
output a hibernation exit signal based on a result of comparing the first input signal and the second input signal, and
provide the hibernation exit signal to a power management unit (PMU).
20. The semiconductor circuit of claim 17 , further comprising:
a low pass filter configured to,
receive the first input signal and the second input signal from the host,
perform a low pass filter operation on the first input signal and the second input signal, and then
provide the first input signal and the second input signal to the clocked comparator.