Enhanced managed runtime environments that support deterministic record and replay
A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically, and wherein the plurality of instruction units includes one or more memory modification instructions; in response to executing an instruction to commit inserted into the plurality of instructions units, incrementally commit a portion of the one or more memory modification instructions that have been atomically executed so far; and subsequent to incrementally committing the portion of the memory modification instructions that have been atomically executed so far, continue atomic execution of the plurality of instruction units. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.
1. A system comprising:
a processor configured to:
initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically, and wherein the plurality of instruction units includes one or more memory modification instructions;
in response to executing a first instruction to commit inserted by a runtime environment into the plurality of instruction units, invoke a trap handler, wherein the trap handler incrementally commits memory modification instructions that have been atomically executed since a previous time data was committed;
in response to the trap handler returning:
continue atomic execution of the plurality of instruction units; and
insert, by the runtime environment, a second instruction to commit; and
in response to detecting an atomicity terminating event, revert memory operations carried out between the first instruction to commit inserted by the runtime environment and the atomicity terminating event; and
a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.
2. The system of claim 1 wherein the trap handler clears one or more memory markers.
3. The system of claim 1 wherein the trap handler records information associated with instructions that have been atomically executed so far.
4. The system of claim 1 wherein the atomicity terminating event is triggered by a memory access by another processor.
5. The system of claim 1 wherein the processor is further configured to, subsequent to reverting the memory operations carried out between the first instruction to commit and the atomicity terminating event, re-initiate atomic execution.
6. A method comprising:
initiating atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically, and wherein the plurality of instruction units includes one or more memory modification instructions;
in response to executing a first instruction to commit inserted by a runtime environment into the plurality of instruction units, invoking a trap handler, wherein the trap handler incrementally commits memory modification instructions that have been atomically executed since a previous time data was committed;
in response to the trap handler returning:
continuing atomic execution of the plurality of instruction units; and
inserting, by the runtime environment, a second instruction to commit and in response to detecting an atomicity terminating event, reverting memory operations carried out between the first instruction to commit inserted by the runtime environment and the atomicity terminating event.
7. The method of claim 6 wherein the trap handler clears one or more memory markers.
8. The method of claim 6 wherein the trap handler records information associated with instructions that have been atomically executed so far.
9. The method of claim 6 wherein the atomicity terminating event is triggered by a memory access by another processor.
10. The method of claim 6 further comprising, subsequent to reverting the memory operations carried out between the first instruction to commit and the atomicity terminating event, re-initiating atomic execution.
11. A computer program product embodied in a non-transitory computer readable storage medium and comprising computer instructions for:
initiating atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically, and wherein the plurality of instruction units includes one or more memory modification instructions;
in response to executing a first instruction to commit inserted by a runtime environment into the plurality of instruction units, invoking a trap handler, wherein the trap handler incrementally commits memory modification instructions that have been atomically executed since a previous time data was committed;
in response to the trap handler returning:
continuing atomic execution of the plurality of instruction units; and
inserting, by the runtime environment, a second instruction to commit; and
in response to detecting an atomicity terminating event, reverting memory operations carried out between the first instruction to commit inserted by the runtime environment and the atomicity terminating event.