Circuit assignment within reconfigurable device based on predicted shortest processing completion time

1. An information processing apparatus, comprising:

a reconfiguration device which includes a plurality of areas in which a logic can be programmed, and which can change a circuit configuration by performing a dynamic partial reconfiguration on the areas; and

a controller which determines, when arranging, in the reconfiguration device in which a first processing circuit for executing a first task in execution is arranged, a second processing circuit for executing a second task different from the first task, a circuit assignment of the first processing circuit and the second processing circuit with respect to an arrangeable area as a result of combining an using area for the first processing circuit and a space area in the plurality of areas of the reconfiguration device, based on a predicted end time until completion of the processing remaining for both the first task and the second task in a case of the first task and the second task being executed together, and arranges the first processing circuit and the second processing circuit in the reconfiguration device in accordance with the determined circuit assignment,

the controller determines the circuit assignment of the first processing circuit and the second processing circuit based on a combination for which the predicted end time becomes the shortest among combinations of the first processing circuit and the second processing circuit capable of being arranged in the arrangeable area.

2. The information processing apparatus according to claim 1 , wherein when there are a plurality of the first tasks in execution, the controller changes the first processing circuit for executing the first task which does not exert an influence with respect to a processing time of the first task in execution even if the first processing circuit is changed to the first processing circuit with low performance to increase a space area in the plurality of areas of the reconfiguration device, and then determines the circuit assignment of the first processing circuit and the second processing circuit.

3. The information processing apparatus according to claim 1 , wherein when there is the first task which uses a processing circuit same as a processing circuit for executing the second task, the circuit assignment of the first processing circuit and the second processing circuit is determined based on the predicted end time of the first and second task and a time taken for the circuit arrangement.

4. An information processing method of an information processing apparatus including a reconfiguration device which includes a plurality of areas in which a logic can be programmed, and which can change a circuit configuration by performing a dynamic partial reconfiguration on the areas, the information processing method comprising:

determining, when arranging, in the reconfiguration device in which a first processing circuit for executing a first task in execution is arranged, a second processing circuit for executing a second task different from the first task, a circuit assignment of the first processing circuit and the second processing circuit with respect to an arrangeable area as a result of combining an using area for the first processing circuit and a space area in the plurality of areas of the reconfiguration device, based on a predicted end time until completion of the processing remaining for both the first task and the second task in a case of the first task and the second task executed together; and

arranging the first processing circuit and the second processing circuit in the reconfiguration device in accordance with the determined circuit assignment,

determines the circuit assignment of the first processing circuit and the second processing circuit based on a combination for which the predicted end time becomes the shortest among combinations of the first processing circuit and the second processing circuit capable of being arranged in the arrangeable area.

5. A non-transitory computer-readable recording medium which records a program for causing a computer of an information processing apparatus including a reconfiguration device which includes a plurality of areas in which a logic can be programmed, and which can change a circuit configuration by performing a dynamic partial reconfiguration on the areas, to execute:

processing of determining, when arranging, in the reconfiguration device in which a first processing circuit for executing a first task in execution is arranged, a second processing circuit for executing a second task different from the first task, a circuit assignment of the first processing circuit and the second processing circuit with respect to an arrangeable area as a result of combining an using area for the first processing circuit and a space area in the plurality of areas of the reconfiguration device, based on a predicted end time until completion of the processing remaining for both the first task and the second task in a case of the first task and the second task executed together; and

processing of arranging the first processing circuit and the second processing circuit in the reconfiguration device in accordance with the determined circuit assignment,

the processing of determining determines the circuit assignment of the first processing circuit and the second processing circuit based on a combination for which the predicted end time becomes the shortest among combinations of the first processing circuit and the second processing circuit capable of being arranged in the arrangeable area.