Application-specific processor generation from general purpose processors

1. A method for tailoring a bespoke processor, the method comprising:

generating, via a processing system, first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application by performing symbolic simulation, where unknown input values are represented as Xs, to identify unusable gates of the general purpose processor design; and

gate cutting and stitching, via the processing system, based on the first gate-level activity information to remove unusable gates from the general purpose processor design and reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application.

2. The method of claim 1 , wherein performing symbolic simulation comprises:

initializing a list of unusable gates as all gates of the general purpose processor design;

initializing all inputs of the general purpose processor design to Xs, where each X represents an unknown logic value;

simulating the first target application on the general purpose processor design; and

removing each gate that toggles and each gate through which an X propagates during the simulation from the list of unusable gates.

3. The method of claim 1 , further comprising:

generating a list of unusable gates based on the first gate-level activity information,

wherein performing gate cutting and stitching comprises:

removing each gate on the list of unusable gates from a gate-level netlist of the general purpose processor design;

tying fanout locations that were connected to the output net of each removed gate to a static voltage corresponding to the constant output value of the gate observed while generating the first gate-level activity information;

re-synthesizing the gate-level netlist after removing unusable gates; and

placing and routing the re-synthesized netlist to produce the bespoke processor design.

4. The method of claim 3 , wherein re-synthesizing the netlist comprises at least one of the following:

replacing gates having constant inputs by simpler gates;

removing toggled gates left with floating outputs; and

replacing higher power cells of logic paths having extra timing slack with smaller, lower power versions of the cells.

5. A method for tailoring a bespoke processor, the method comprising:

generating, via a processing system, first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application by performing symbolic simulation to identify unusable gates of the general purpose processor design; and

gate cutting and stitching, via the processing system, based on the first gate-level activity information to remove unusable gates from the general purpose processor design and reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application;

wherein performing symbolic simulation comprises:

initializing a list of unusable gates as all gates of the general purpose processor design;

initializing all inputs of the general purpose processor design to Xs, where each X represents an unknown logic value;

simulating the first target application on the general purpose processor design;

removing each gate that toggles and each gate through which an X propagates during the simulation from the list of unusable gates;

tracking the most conservative gate-level state that has been observed for each conditional branch encountered during the simulation; and

in response to re-encountering a conditional branch while simulating on a control flow path:

terminating simulation down the control flow path in response to the symbolic state being simulated being a substate of the most conservative gate-level state previously observed at the conditional branch; and

in response to the symbolic state being simulated not being a substate of the most conservative gate-level state previously observed at the conditional branch, merging the symbolic state being simulated with the most conservative gate-level state previously observed at the conditional branch to create an updated most conservative gate-level state for the conditional branch, and continuing simulation from the updated most conservative gate-level state.

6. A method for tailoring a bespoke processor, the method comprising:

generating, via a processing system, first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application;

gate cutting and stitching, via the processing system, based on the first gate-level activity information to remove unusable gates from the general purpose processor design and reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application; and

generating, via the processing system, second gate-level activity information of the general purpose processor design for all possible executions of a second target application for any possible inputs to the second target application,

wherein gate cutting and stitching comprises gate cutting and stitching based on the intersection of the first gate-level activity information and the second gate-level activity information to remove unusable gates from the general purpose processor design and reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application and the second target application.

7. A method for tailoring a bespoke processor, the method comprising:

generating, via a processing system, first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application;

gate cutting and stitching, via the processing system, based on the first gate-level activity information to remove unusable gates from the general purpose processor design and reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application; and

generating, via the processing system, second gate-level activity information of the general purpose processor design for all possible executions of a set of instructions for any possible inputs to the set of instructions,

wherein gate cutting and stitching comprises gate cutting and stitching based on the intersection of the first gate-level activity information and the second gate-level activity information to remove unusable gates from the general purpose processor design and reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application and the set of instructions.

8. The method of claim 7 , wherein the set of instructions comprises a Turing complete set of instructions.

9. The method of claim 7 , further comprising:

fabricating a bespoke processor based on the bespoke processor design.

10. A system comprising:

a machine readable storage medium storing instructions; and

a processor to execute the instructions to:

generate first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application by performing symbolic simulation, where unknown input values are represented as Xs, to identify unusable gates of the general purpose processor design;

remove unusable gates from the general purpose processor design based on the first gate-level activity information; and

reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application.

11. The system of claim 10 , wherein the processor executes the instructions to perform the symbolic simulation to:

initialize a list of unusable gates as all gates of the general purpose processor design;

initialize all inputs of the general purpose processor design to Xs, where each X represents an unknown logic value;

simulate the first target application on the general purpose processor design; and

remove each gate that toggles and each gate through which an X propagates during the simulation from the list of unusable gates.

12. The system of claim 10 , wherein the processor executes the instructions to further:

generate a list of unusable gates based on the first gate-level activity information;

remove each gate on the list of unusable gates from a gate-level netlist of the general purpose processor design;

tie fanout locations that were connected to the output net of each removed gate to a static voltage corresponding to the constant output value of the gate observed while generating the first gate-level activity information;

re-synthesize the gate-level netlist after removing all unusable gates; and

place and route the re-synthesized netlist to produce the bespoke processor design.

13. The system of claim 12 , wherein the processor executes the instructions to re-synthesize the gate-level netlist to:

replace gates having constant inputs by simpler gates;

remove toggled gates left with floating outputs; and

replace higher power cells of logic paths having extra timing slack with smaller, lower power versions of the cells.

14. A system comprising:

a machine readable storage medium storing instructions; and

a processor to execute the instructions to:

generate first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application by performing symbolic simulation to identify unusable gates of the general purpose processor design;

remove unusable gates from the general purpose processor design based on the first gate-level activity information; and

reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application,

wherein the processor executes the instructions to perform the symbolic simulation to:

initialize a list of unusable gates as all gates of the general purpose processor design;

initialize all inputs of the general purpose processor design to Xs, where each X represents an unknown logic value;

simulate the first target application on the general purpose processor design;

remove each gate that toggles and each gate through which an X propagates during the simulation from the list of unusable gates;

track the most conservative gate-level state that has been observed for each conditional branch encountered during the simulation; and

in response to re-encountering a conditional branch while simulating on a control flow path:

terminate simulation down the control flow path in response to the symbolic state being simulated being a substate of the most conservative gate-level state previously observed at the conditional branch; and

in response to the symbolic state being simulated not being a substate of the most conservative gate-level state previously observed at the conditional branch, merge the symbolic state being simulated with the most conservative gate-level state previously observed at the conditional branch to create an updated most conservative gate-level state for the conditional branch, and continue simulation from the updated most conservative gate-level state.

15. A system comprising:

a machine readable storage medium storing instructions; and

a processor to execute the instructions to:

generate first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application;

remove unusable gates from the general purpose processor design based on the first gate-level activity information;

reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application;

generate second gate-level activity information of the general purpose processor design for all possible executions of a second target application for any possible inputs to the second target application;

remove unusable gates from the general purpose processor design based on the intersection of the first gate-level activity information and the second gate-level activity information; and

reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application and the second target application.

16. A system comprising:

a machine readable storage medium storing instructions; and

a processor to execute the instructions to:

generate first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application;

remove unusable gates from the general purpose processor design based on the first gate-level activity information;

reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application;

generate second gate-level activity information of the general purpose processor design for all possible executions of a set of instructions for any possible inputs to the set of instructions;

remove unusable gates from the general purpose processor design based on the intersection of the first gate-level activity information and the second gate-level activity information; and

reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application and the set of instructions.

17. The system of claim 16 , wherein the set of instructions comprises a Turing complete set of instructions.