Nonvolatile digital computing with ferroelectric FET
Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I DS −V G hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two I DS states at V G =0.
1. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias, wherein:
the circuit topology is configured as a backup and restore circuit (B&R circuit);
the B&R circuit comprising:
a first transistor, M 1 , M 1 having an M 1 -source, an M 1 -gate, and an M 1 -drain;
a second transistor, M 2 , M 2 having an M 2 -source, an M 2 -gate, and an M 2 -drain;
a third transistor, M 3 , M 3 having an M 3 -source, an M 3 -gate, and an M 3 -drain;
a fourth transistor, M 4 , M 4 having an M 4 -source, an M 4 -gate, and an M 4 -drain;
a fifth transistor, M 5 , M 5 having an M 5 -source, an M 5 -gate, and an M 5 -drain;
a sixth transistor, M 6 , M 6 having an M 6 -source, an M 6 -gate, and an M 6 -drain;
a seventh transistor, M 7 , M 7 having an M 7 -source, an M 7 -gate, and an M 7 -drain;
an eighth transistor, M 8 , M 8 having an M 8 -source, an M 8 -gate, and an M 8 -drain;
a first branch and a second branch, the first branch including M 1 , M 2 , M 5 , M 7 , and a ground, GND, the second branch including M 3 , M 4 , M 6 , and M 8 ;
each of M 1 , M 2 , M 3 , M 4 , M 7 , and M 8 is a metal-oxide-semiconductor field-effect transistor (MOSFET) and each of M 5 and M 6 is a FeFET;
M 1 -gate being connected to a backup control signal input, B kp_input and M 3 -gate;
M 1 -drain being connected to M 2 -drain;
M 1 -drain being configured to be connected to a slave latch via the first branch;
M 1 -source being connected to M 5 -source and M 7 -drain;
M 2 -drain being connected to M 1 -drain;
M 2 -drain being configured to be connected to the slave latch via the first branch;
M 2 -gate being connected to a backup and restore control signal input, B kp +R str and M 3 -gate;
M 2 -source being connected to M 6 -gate, M 5 -drain, M 5 -gate, M 6 -drain, and M 3 -source;
M 3 -drain being connected to M 4 -drain;
M 3 -drain being configured to be connected to the slave latch via the second branch;
M 3 -gate being connected to B kp +R str and M 1 -gate;
M 3 -source being connected to M 5 -gate, M 6 -drain, M 5 -drain, M 2 -source, and M 6 -gate;
M 4 -drain being connected to M 3 -drain;
M 4 -drain being configured to be connected to the slave latch via the second branch;
M 4 -gate being connected to a backup control signal output, B kp_output ;
M 4 -source being connected to M 6 -source and M 8 -drain;
M 5 -drain being connected to M 2 -source, M 5 -gate, M 6 -gate, M 6 -drain, and M 3 -source;
M 5 -gate being connected to M 3 -source, M 6 -drain, M 6 -gate, M 2 -source, and M 5 -drain;
M 5 -source being connected to M 7 -drain and M 1 -source;
M 6 -drain being connected to M 3 -source, M 5 -gate, M 6 -gate, M 5 -drain, and M 2 -source;
M 6 -gate being connected to M 2 -source, M 5 -drain, M 5 -gate, M 6 -drain, and M 3 -source;
M 6 -source being connected to M 4 -source and M 8 -drain;
M 7 -drain being connected to M 1 -source and M 5 -source;
M 7 -gate being connected to a restore input control signal, R str ;
M 7 -source being connected to GND via the first branch;
M 8 -drain being connected to M 4 -source and M 6 -source;
M 8 -gate being connected to M 7 -gate; and
M 8 -source being connected to GND via the second branch.
2. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias, wherein:
the circuit topology is configured as a D-Flip Flop (DFF);
the DFF comprising a master latch, a slave latch, and a backup and restore circuit (B&R circuit);
the master latch comprising:
a first master inverter M INV1 , a second master inverter, M INV2 , a third master inverter, M INV3 , and a master transmission gate, M GATE ;
input of M INV1 being connected to a data input signal, D;
output of M INV1 being connected to input of M INV2 ,
input of M INV2 being connected to output of M INV1 ,
output of M INV2 being connected to input of M INV3 ,
input of M INV3 being connected to output of M INV2 ,
output of M INV3 being connected to input of M GATE ;
input of M GATE being connected to output of M INV3 ; and
output of M GATE being connected to input of M INV2 and output of M INV1 ;
the slave latch comprising:
a first slave inverter, S INV1 , a second slave inverter, S INV2 , a third slave inverter, S INV3 , and a slave transmission gate, S GATE ;
input of S INV2 being connected to output of M INV2 ;
input of S INV2 being connected to output of S INV1 ;
output of S INV2 being connected to input of S INV3 and to a data output Q;
input of S INV3 being connected to output of S INV2 ;
output of S INV3 being connected to input of S GATE ; and
output of S GATE being connected to input of S INV2 and output of S INV1 ; and
the B&R circuit comprising:
a first transistor, M 1 , M 1 having an M 1 -source, an M 1 -gate, and an M 1 -drain;
a second transistor, M 2 , M 2 having an M 2 -source, an M 2 -gate, and an M 2 -drain;
a third transistor, M 3 , M 3 having an M 3 -source, an M 3 -gate, and an M 3 -drain;
a fourth transistor, M 4 , M 4 having an M 4 -source, an M 4 -gate, and an M 4 -drain;
a fifth transistor, M 5 , M 5 having an M 5 -source, an M 5 -gate, and an M 5 -drain;
a sixth transistor, M 6 , M 6 having an M 6 -source, an M 6 -gate, and an M 6 -drain;
a seventh transistor, M 7 , M 7 having an M 7 -source, an M 7 -gate, and an M 7 -drain;
an eighth transistor, M 8 , M 8 having an M 8 -source, an M 8 -gate, and an M 8 -drain;
a first branch and a second branch, the first branch including M 1 , M 2 , M 5 , M 7 , and a ground, GND, the second branch including M 3 , M 4 , M 6 , and M 8 ;
each of M 1 , M 2 , M 3 , M 4 , M 7 , and M 8 is a metal-oxide-semiconductor field-effect transistor (MOSFET) and each of M 5 and M 6 is a FeFET;
M 1 -gate is connected to a backup control signal input, B kp_input and M 3 -gate;
M 1 -drain is connected to M 2 -drain;
M 1 -drain is configured to be connected to the slave latch via the first branch;
M 1 -source is connected to M 5 -source and M 7 -drain;
M 2 -drain is connected to M 1 -drain;
M 2 -drain is configured to be connected to the slave latch via the first branch;
M 2 -gate is connected to a backup and restore control signal input, B kp +R str and M 3 -gate;
M 2 -source is connected to M 6 -gate, M 5 -drain, M 5 -gate, M 6 -drain, and M 3 -source;
M 3 -drain is connected to M 4 -drain;
M 3 -drain is configured to be connected to the slave latch via the second branch;
M 3 -gate is connected to B kp +R str and M 1 -gate;
M 3 -source is connected to M 5 -gate, M 6 -drain, M 5 -drain, M 2 -source, and M 6 -gate;
M 4 -drain is connected to M 3 -drain;
M 4 -drain is configured to be connected to the slave latch via the second branch;
M 4 -gate is connected to a backup control signal output, B kp_output ;
M 4 -source is connected to M 6 -source and M 8 -drain;
M 5 -drain is connected to M 2 -source, M 5 -gate, M 6 -gate, M 6 -drain, and M 3 -source;
M 5 -gate is connected to M 3 -source, M 6 -drain, M 6 -gate, M 2 -source, and M 5 -drain;
M 5 -source is connected to M 7 -drain and M 1 -source;
M 6 -drain is connected to M 3 -source, M 5 -gate, M 6 -gate, M 5 -drain, and M 2 -source;
M 6 -gate is connected to M 2 -source, M 5 -drain, M 5 -gate, M 6 -drain, and M 3 -source;
M 6 -source is connected to M 4 -source and M 8 -drain;
M 7 -drain is connected to M 1 -source and M 5 -source;
M 7 -gate is connected to a restore input control signal, R str ;
M 7 -source is connected to GND via the first branch;
M 8 -drain is connected to M 4 -source and M 6 -source;
M 8 -gate is connected to M 7 -gate; and
M 8 -source is connected to GND via the second branch.
3. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias, wherein:
the circuit topology is configured as a latch configured to have an input D;
the latch comprising:
a first transistor, M 1 , M 1 having an M 1 -source, an M 1 -gate, and an M 1 -drain;
a second transistor, M 2 , M 2 having an M 2 -source, an M 2 -gate, and an M 2 -drain;
a third transistor, M 3 , M 3 having an M 3 -source, an M 3 -gate, and an M 3 -drain;
a fourth transistor, M 4 , M 4 having an M 4 -source, an M 4 -gate, and an M 4 -drain;
a fifth transistor, M 5 , M 5 having an M 5 -source, an M 5 -gate, and an M 5 -drain;
a sixth transistor, M 6 , M 6 having an M 6 -source, an M 6 -gate, and an M 6 -drain;
a seventh transistor, M 7 , M 7 having an M 7 -source, an M 7 -gate, and an M 7 -drain;
an eighth transistor, M 8 , M 8 having an M 8 -source, an M 8 -gate, and an M 8 -drain;
a ninth transistor, M 9 , M 9 having an M 9 -source, an M 9 -gate, and an M 9 -drain;
a tenth transistor, M 10 , M 10 having an M 10 -source, an M 10 -gate, and an M 10 -drain;
an eleventh transistor, M 11 , M 11 having an M 11 -source, an M 11 -gate, and an M 11 -drain;
a twelfth transistor, M 12 , M 12 having an M 12 -source, an M 12 -gate, and an M 12 -drain;
a thirteenth transistor, M 5b , M 5b having an M 5b -source, an M 5b -gate, and an M 5b -drain;
a fourteenth transistor, M 6b , M 6b having an M 6b -source, an M 6b -gate, and an M 6b -drain;
each of M 1 , M 2 , M 3 , M 4 , M 7 , M 8 , M 9 , M 10 , and M 11 is a metal oxide semiconductor field effect transistor (MOSFET);
each of M 5 and M 6 is a FeFET;
M 1 -drain being connected to M 2 -drain and a data input D;
M 1 -gate being connected to a clock driver, CLK;
M 1 -source being connected to M 2 -source, M 3 -gate, M 5 -gate, M 7 -gate, M 11 -source, M 12 -source, M 3 -source, M 9 -source, M 10 -source, M 5 -drain, and M 5b -drain;
M 2 -drain being connected to M 1 -drain and data input D;
M 2 -gate being connected to CLK;
M 2 -source being connected to M 1 -source, M 3 -gate, M 5 -gate, M 7 -gate, M 11 -source, M 12 -source, M 3 -source, M 9 -source, M 10 -source, M 5 -drain, and M 5b -drain;
M 3 -drain being connected to a voltage supply, V DD ;
M 3 -gate being connected to M 1 -source, M 2 -source, M 5 -gate, M 7 -gate, M 11 -source, M 12 -source, M 3 -source, M 9 -source, M 10 -source, M 5 -drain, and M 5b -drain;
M 3 -source can be connected to M 1 -source, M 2 -source, M 5 -gate, M 7 -gate, M 11 -source, M 12 -source, M 3 -gate, M 9 -source, M 10 -source, M 5 -drain, and M 5b -drain;
M 4 -drain being connected to V DD ;
M 4 -gate being connected to a data output QN, a data output Q, M 6 -gate, M 8 -gate, M 4 -source, M 9 -drain, M 10 -drain, M 11 -drain, M 12 -drain, M 6b -drain, and M 6 -drain;
M 4 -source being connected to data output QN, data output Q, M 6 -gate, M 8 -gate, M 4 -gate, M 9 -drain, M 10 -drain, M 11 -drain, M 12 -drain, M 6b -drain, and M 6 -drain;
M 5 -drain being connected to M 1 -source, M 2 -source, M 5 -gate, M 7 -gate, M 11 -source, M 12 -source, M 3 -source, M 9 -source, M 10 -source, and M 5b -drain;
M 5 -gate being connected to M 1 -source, M 2 -source, M 5 -drain, M 7 -gate, M 11 -source, M 12 -source, M 3 -source, M 9 -source, M 10 -source, M 5b -gate, and M 5b -drain;
M 5 -source being connected to M 7 -drain;
M 5b -drain being connected to M 1 -source, M 2 -source, M 5 -gate, M 7 -gate, M 11 -source, M 12 -source, M 3 -source, M 9 -source, M 10 -source, and M 5 -drain;
M 5b -gate being connected to M 5 -gate;
M 5b -source being connected to ground, GND;
M 6 -drain being connected to data output QN, data output Q, M 6 -gate, M 8 -gate, M 4 -source, M 9 -drain, M 10 -drain, M 11 -drain, M 12 -drain, M 6b -drain, and M 4 -gate;
M 6 -gate being connected to data output QN, data output Q, M 6 -drain, M 6b -gate, M 8 -gate, M 4 -source, M 9 -drain, M 10 -drain, M 11 -drain, M 12 -drain, M 6b -drain, and M 4 -gate;
M 6 -source being connected to M 8 -drain;
M 6b -drain being connected to data output QN, data output Q, M 6 -gate, M 8 -gate, M 4 -source, M 9 -drain, M 10 -drain, M 11 -drain, M 12 -drain, M 4 -gate, and M 6 -drain;
M 6b -gate being connected to M 6 -gate;
M 6b -source being connected to GND;
M 7 -drain being connected to M 5 -source;
M 7 -gate being connected to M 1 -source, M 2 -source, M 5 -gate, M 5 -drain, M 11 -source, M 12 -source, M 3 -source, M 9 -source, M 10 -source, and M 5b -drain;
M 7 -source being connected to GND;
M 8 -drain being connected to M 6 -source;
M 8 -gate being connected to data output QN, data output Q, M 6 -gate, M 4 -gate, M 4 -source, M 9 -drain, M 10 -drain, M 11 -drain, M 12 -drain, M 6b -drain, and M 6 -drain, M 8 -source can be connected to GND;
M 9 -drain being connected to data output QN, data output Q, M 6 -gate, M 8 -gate, M 4 -source, M 4 -gate, M 10 -drain, M 11 -drain, M 12 -drain, M 6b -drain, and M 6 -drain;
M 9 -gate being connected to V DD ;
M 9 -source being connected to M 1 -source, M 2 -source, M 5 -gate, M 7 -gate, M 11 -source, M 12 -source, M 3 -source, M 5 -drain, M 10 -source, and M 5b -drain;
M 10 -drain being connected to data output QN, data output Q, M 6 -gate, M 8 -gate, M 4 -source, M 9 -drain, M 4 -gate, M 11 -drain, M 12 -drain, M 6b -drain, and M 6 -drain;
M 10 -gate being connected to GND;
M 10 -source being connected to M 1 -source, M 2 -source, M 5 -gate, M 7 -gate, M 11 -source, M 12 -source, M 3 -source, M 9 -source, M 5 -drain, and M 5b -drain;
M 11 -drain being connected to data output QN, data output Q, M 6 -gate, M 8 -gate, M 4 -source, M 9 -drain, M 10 -drain, M 4 -gate, M 12 -drain, M 6b -drain, and M 6 -drain;
M 11 -gate being connected to CLK;
M 11 -source being connected to M 1 -source, M 2 -source, M 5 -gate, M 7 -gate, M 5 -drain, M 12 -source, M 3 -source, M 9 -source, M 10 -source, and M 5b -drain;
M 12 -drain being connected to data output QN, data output Q, M 6 -gate, M 8 -gate, M 4 -source, M 9 -drain, M 10 -drain, M 11 -drain, M 4 -gate, M 6b -drain, and M 6 -drain;
M 12 -gate being connected to CLK; and
M 12 -source being connected to M 1 -source, M 2 -source, M 5 -gate, M 7 -gate, M 11 -source, M 5 -drain, M 3 -source, M 9 -source, M 10 -source, and M 5b -drain.
4. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias, wherein:
the circuit topology is configured as a latch configured to have a differential-driving input pair D/DN;
the latch comprising:
a first transistor, M 1 , M 1 having an M 1 -source, an M 1 -gate, and an M 1 -drain;
a second transistor, M 2 , M 2 having an M 2 -source, an M 2 -gate, and an M 2 -drain;
a third transistor, M 3 , M 3 having an M 3 -source, an M 3 -gate, and an M 3 -drain;
a fourth transistor, M 4 , M 4 having an M 4 -source, an M 4 -gate, and an M 4 -drain;
a fifth transistor, M 5 , M 5 having an M 5 -source, an M 5 -gate, and an M 5 -drain;
a sixth transistor, M 6 , M 6 having an M 6 -source, an M 6 -gate, and an M 6 -drain;
a seventh transistor, M 7 , M 7 having an M 7 -source, an M 7 -gate, and an M 7 -drain;
an eighth transistor, M 8 , M 8 having an M 8 -source, an M 8 -gate, and an M 8 -drain;
each of M 1 , M 2 , M 3 , M 4 , M 7 , and M 8 is a metal oxide semiconductor field effect transistor (MOSFET);
each of M 5 and M 6 is a FeFET;
M 1 -drain being connected to a data input D;
M 1 -gate being connected to a clock driver, CLK;
M 1 -source being connected to M 5 -gate, M 3 -gate, M 5 -source, M 2 -source, M 7 -gate, M 7 -drain, a data output Q, a data output QN, M 6 -source, M 8 -drain, M 8 -gate, M 6 -gate, and M 4 -gate;
M 2 -drain being connected to data input DN;
M 2 -gate being connected to M 1 -gate;
M 2 -source being connected to M 5 -gate, M 3 -gate, M 5 -source, M 1 -source, M 7 -gate, M 7 -drain, a data output Q, a data output QN, M 6 -source, M 8 -drain, M 8 -gate, M 6 -gate, and M 4 -gate;
M 3 -drain being connected to a voltage supply, V DD ;
M 3 -gate being connected to M 5 -gate, M 1 -source, M 5 -source, M 2 -source, M 7 -gate, M 7 -drain, data output Q, data output QN, M 6 -source, M 8 -drain, M 8 -gate, M 6 -gate, and M 4 -gate;
M 3 -source being connected to M 5 -drain;
M 4 -drain being connected to V DD ;
M 4 -gate being connected to M 5 -gate, M 3 -gate, M 5 -source, M 2 -source, M 7 -gate, M 7 -drain, data output Q, data output QN, M 6 -source, M 8 -drain, M 8 -gate, M 6 -gate, and M 1 -source;
M 4 -source being connected to M 6 -drain;
M 5 -drain being connected to M 3 -source;
M 5 -gate being connected to M 1 -source, M 3 -gate, M 5 -source, M 2 -source, M 7 -gate, M 7 -drain, data output Q, data output QN, M 6 -source, M 8 -drain, M 8 -gate, M 6 -gate, and M 4 -gate;
M 5 -source being connected to M 5 -gate, M 3 -gate, M 1 -source, M 2 -source, M 7 -gate, M 7 -drain, data output Q, data output QN, M 6 -source, M 8 -drain, M 8 -gate, M 6 -gate, and M 4 -gate;
M 6 -drain being connected to M 4 -source;
M 6 -gate being connected to M 5 -gate, M 3 -gate, M 5 -source, M 2 -source, M 7 -gate, M 7 -drain, data output Q, data output QN, M 6 -source, M 8 -drain, M 8 -gate, M 1 -source, and M 4 -gate;
M 6 -source being connected to M 5 -gate, M 3 -gate, M 5 -source, M 2 -source, M 7 -gate, M 7 -drain, data output Q, data output QN, M 1 -source, M 8 -drain, M 8 -gate, M 6 -gate, and M 4 -gate;
M 7 -drain being connected to M 5 -gate, M 3 -gate, M 5 -source, M 2 -source, M 7 -gate, M 1 -source, data output Q, data output QN, M 6 -source, M 8 -drain, M 8 -gate, M 6 -gate, and M 4 -gate;
M 7 -gate being connected to M 5 -gate, M 3 -gate, M 5 -source, M 2 -source, M 1 -source, M 7 -drain, data output Q, data output QN, M 6 -source, M 8 -drain, M 8 -gate, M 6 -gate, and M 4 -gate;
M 7 -source being connected to ground, GND;
M 8 -drain being connected to M 5 -gate, M 3 -gate, M 5 -source, M 2 -source, M 7 -gate, M 7 -drain, data output Q, data output QN, M 6 -source, M 1 -source, M 8 -gate, M 6 -gate, and M 4 -gate;
M 8 -gate being connected to M 5 -gate, M 3 -gate, M 5 -source, M 2 -source, M 7 -gate, M 7 -drain, data output Q, data output QN, M 6 -source, M 8 -drain, M 1 -source, M 6 -gate, and M 4 -gate; and
M 8 -source being connected to GND.
5. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias, wherein:
the circuit topology is configured as a latch configured to have a differential-driving input pair D/DN;
the latch comprising:
a first transistor, M 1 , M 1 having an M 1 -source, an M 1 -gate, and an M 1 -drain;
a second transistor, M 2 , M 2 having an M 2 -source, an M 2 -gate, and an M 2 -drain;
a third transistor, M 3 , M 3 having an M 3 -source, an M 3 -gate, and an M 3 -drain;
a fourth transistor, M 4 , M 4 having an M 4 -source, an M 4 -gate, and an M 4 -drain;
a fifth transistor, M 5 , M 5 having an M 5 -source, an M 5 -gate, and an M 5 -drain;
a sixth transistor, M 6 , M 6 having an M 6 -source, an M 6 -gate, and an M 6 -drain;
a seventh transistor, M 7 , M 7 having an M 7 -source, an M 7 -gate, and an M 7 -drain;
an eighth transistor, M 8 , M 8 having an M 8 -source, an M 8 -gate, and an M 8 -drain;
a ninth transistor, M 9 , M 9 having an M 9 -source, an M 9 -gate, and an M 9 -drain;
a tenth transistor, M 10 , M 10 having an M 10 -source, an M 10 -gate, and an M 10 -drain;
each of M 1 , M 2 , M 3 , M 4 , M 9 , and M 10 is a metal oxide semiconductor field effect transistor (MOSFET);
each of M 5 , M 6 , M 7 , and M 8 is a FeFET;
M 1 -drain being connected to a data input D;
M 1 -gate being connected to a clock driver, CLK;
M 1 -source being connected to M 5 -gate, M 3 -gate, M 2 -source, M 7 -gate, M 9 -gate, M 5 -source, M 6 -source, a data output Q, M 6 -gate, M 4 -gate, M 7 -drain, M 8 -drain, a data output QN, M 8 -gate, and M 10 -gate;
M 2 -drain being connected to a data input DN;
M 2 -gate being connected to M 1 -gate;
M 2 -source being connected to M 5 -gate, M 3 -gate, M 1 -source, M 7 -gate, M 9 -gate, M 5 -source, M 6 -source, data output Q, M 6 -gate, M 4 -gate, M 7 -drain, M 8 -drain, data output QN, M 8 -gate, and M 10 -gate;
M 3 -drain being connected to a voltage supply, V DD ;
M 3 -gate being connected to M 5 -gate, M 1 -source, M 2 -source, M 7 -gate, M 9 -gate, M 5 -source, M 6 -source, data output Q, M 6 -gate, M 4 -gate, M 7 -drain, M 8 -drain, data output QN, M 8 -gate, and M 10 -gate;
M 3 -source being connected to M 5 -drain;
M 4 -drain being connected to V DD ;
M 4 -gate being connected to M 5 -gate, M 3 -gate, M 2 -source, M 7 -gate, M 9 -gate, M 5 -source, M 6 -source, data output Q, M 6 -gate, M 1 -source, M 7 -drain, M 8 -drain, data output QN, M 8 -gate, and M 10 -gate;
M 4 -source being connected to M 6 -drain;
M 5 -drain being connected to M 3 -source;
M 5 -gate c being connected to M 1 -source, M 3 -gate, M 2 -source, M 7 -gate, M 9 -gate, M 5 -source, M 6 -source, data output Q, M 6 -gate, M 4 -gate, M 7 -drain, M 8 -drain, data output QN, M 8 -gate, and M 10 -gate;
M 5 -source being connected to M 5 -gate, M 3 -gate, M 2 -source, M 7 -gate, M 9 -gate, M 1 -source, M 6 -source, data output Q, M 6 -gate, M 4 -gate, M 7 -drain, M 8 -drain, data output QN, M 8 -gate, and M 10 -gate;
M 6 -drain being connected to M 4 -source;
M 6 -gate being connected to M 5 -gate, M 3 -gate, M 2 -source, M 7 -gate, M 9 -gate, M 5 -source, M 6 -source, data output Q, M 1 -source, M 4 -gate, M 7 -drain, M 8 -drain, data output QN, M 8 -gate, and M 10 -gate;
M 6 -source being connected to M 5 -gate, M 3 -gate, M 2 -source, M 7 -gate, M 9 -gate, M 5 -source, M 1 -source, data output Q, M 6 -gate, M 4 -gate, M 7 -drain, M 8 -drain, data output QN, M 8 -gate, and M 10 -gate;
M 7 -drain can be connected to M 5 -gate, M 3 -gate, M 2 -source, M 7 -gate, M 9 -gate, M 5 -source, M 6 -source, data output Q, M 6 -gate, M 4 -gate, M 1 -source, M 8 -drain, data output QN, M 8 -gate, and M 10 -gate;
M 7 -gate can be connected to M 5 -gate, M 3 -gate, M 2 -source, M 1 -source, M 9 -gate, M 5 -source, M 6 -source, data output Q, M 6 -gate, M 4 -gate, M 7 -drain, M 8 -drain, data output QN, M 8 -gate, and M 10 -gate;
M 7 -source can be connected to M 9 -drain;
M 10 -drain can be connected to M 8 -source;
M 10 -gate can be connected to M 5 -gate, M 3 -gate, M 2 -source, M 7 -gate, M 9 -gate, M 5 -source, M 6 -source, data output Q, M 6 -gate, M 4 -gate, M 7 -drain, M 8 -drain, data output QN, M 8 -gate, and M 1 -source; and
M 10 -source can be connected to ground, GND.
6. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias, wherein:
the circuit topology is configured as a plurality of 2-transistor (2T) memory cells arranged in a memory cell array cell;
each 2T-memory cell comprising:
a first transistor T 1 , a second transistor T 2 , a bit line, BL, a first Wordline, WLW, and a second Wordline, WLR;
T 1 being a metal oxide semiconductor field effect transistor (MOSFET) and T 2 being a FeFET;
T 1 having a T 1 -source, a T 1 -gate, and a T 1 -drain;
T 2 having a T 2 -source, a T 2 -gate, and a T 2 -drain;
WLW being configured to receive and/or transmit a write signal for write operations;
WLR being configured to receive and/or transmit a read signal for read operations;
T 2 -drain being connected to BL and WLW;
T 2 -gate being connected to WLW;
T 2 -source being connected to T 1 -drain;
T 1 -gate being connected to WLR and BL; and
T 1 -source being connected to ground, GND;
wherein the memory cell array comprises:
a first 2T-memory cell, a second 2T-memory cell, a third 2T-memory cell, a fourth 2T-memory cell, a fifth 2T-memory cell, a sixth 2T-memory cell, a seventh 2T-memory cell, and an eighth 2T-memory cell, each memory cell having a T 1 and a T 2 , wherein T 1 is a MOSFET and T 2 is a FeEFT, wherein:
the first 2T-memory cell has a first T 1 and a first T 2 ;
the second 2T-memory cell has a second T 1 and a second T 2 ;
the third 2T-memory cell has a third T 1 and a third T 2 ;
the fourth 2T-memory cell has a fourth T 1 and a fourth T 2 ;
the fifth 2T-memory cell has a fifth T 1 and a fifth T 2 ;
the sixth 2T-memory cell 124 has a sixth T 1 and a sixth T 2 ;
the seventh 2T-memory cell has a seventh T 1 and a seventh T 2 ;
the eighth 2T-memory cell 124 has an eighth T 1 and a eighth T 2 ; and
a first BL, BL 1 , a second BL, BL 2 , a third BL, BL 3 , and a fourth BL, BL 4 ;
a first WLW, WLW 1 , a second WLW, WLW 2 , a first WLR, WLR 1 , and a second WLR, WLR 2 , wherein each of WLW 1 and WLW 2 is configured to receive and/or transmit a write signal for write operations, and each of WLR 1 and WLR 2 is configured to receive and/or transmit a read signal for read operations;
the first cell T 2 -drain being connected to BL 1 and WLW 1 ;
the first cell T 2 -gate being connected to WLW 1 ;
the first cell T 2 -source being connected to first cell T 1 -drain;
the first cell T 1 -gate being connected to WLR 1 and BL 1 ;
the first cell T 1 -source being connected to ground, GND;
the second cell T 2 -drain being connected to BL 2 and WLW 1 ;
the second cell T 2 -gate being connected to WLW 1 ;
the second cell T 2 -source being connected to second cell T 1 -drain;
the second cell T 1 -gate being connected to WLR 1 and BL 2 ;
the second cell T 1 -source being connected to GND;
the third cell T 2 -drain being connected to BL 3 and WLW 1 ;
the third cell T 2 -gate being connected to WLW 1 ;
the third cell T 2 -source being connected to third cell T 1 -drain;
the third cell T 1 -gate being connected to WLR 1 and BL 3 ;
the third cell T 1 -source being connected to GND;
the fourth cell T 2 -drain being connected to BL 4 and WLW 1 ;
the fourth cell T 2 -gate being connected to WLW 1 ;
the fourth cell T 2 -source being connected to fourth cell T 1 -drain;
the fourth cell T 1 -gate being connected to WLR 1 and BL 4 ;
the fourth cell T 1 -source being connected to GND;
the fifth cell T 2 -drain being connected to BL 1 and WLW 2 ;
the fifth cell T 2 -gate being connected to WLW 2 ;
the fifth cell T 2 -source being connected to fifth cell T 1 -drain;
the fifth cell T 1 -gate being connected to WLR 2 and BL 1 ;
the fifth cell T 1 -source being connected to GND;
the sixth cell T 2 -drain being connected to BL 2 and WLW 2 ;
the sixth cell T 2 -gate being connected to WLW 2 ;
the sixth cell T 2 -source being connected to sixth cell T 1 -drain;
the sixth cell T 1 -gate being connected to WLR 2 and BL 2 ;
the sixth cell T 1 -source being connected to GND;
the seventh cell T 2 -drain being connected to BL 3 and WLW 2 ;
the seventh cell T 2 -gate being connected to WLW 2 ;
the seventh cell T 2 -source being connected to seventh cell T 1 -drain;
the seventh cell T 1 -gate being connected to WLR 2 and BL 3 ;
the seventh cell T 1 -source being connected to GND;
the eighth cell T 2 -drain being connected to BL 4 and WLW 2 ;
the eighth cell T 2 -gate being connected to WLW 2 ;
the eighth cell T 2 -source being connected to eighth cell T 1 -drain;
the eighth cell T 1 -gate being connected to WLR 2 and BL 4 ; and
the eighth cell T 1 -source being connected to GND.
7. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias, wherein:
the circuit topology is configured as a 3-transistor (3T) memory cell;
the 3T-memory cell comprising:
a first transistor, T 1 , a second transistor, T 2 , a third transistor T 3 , a first bit line, BLW, a second bit line, BLR, a Wordline Write, WLW, a Wordline Read, WLR, and a Wordline-Readline, WLRL;
each of T 1 and T 3 is a metal oxide semiconductor field effect transistor (MOSFET), and T 2 is a FeFET;
T 1 has a T 1 -source, a T 1 -gate, and a T 1 -drain;
T 2 has a T 2 -source, a T 2 -gate, and a T 2 -drain;
T 3 has a T 3 -source, a T 3 -gate, and a T 3 -drain;
T 1 -drain being connected to T 2 -gate;
T 1 -gate being connected to WLW;
T 1 -source being connected to BLW;
T 2 -drain being connected to T 3 -source;
T 2 -gate being connected to T 1 -drain;
T 2 -source being connected to WLRW;
T 3 -drain being connected to BLR;
T 3 -gate being connected to WLR;
T 3 -source being connected to T 2 -drain;
at least one of BLW, WLW, and WLRW being connected to ground, GND; and
WLR being connected to a voltage supply, V DD .
8. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias, wherein:
the circuit topology is configured as a 3-transistor (3T) memory cell;
the 3T-memory cell comprising:
a first transistor, T 1 , a second transistor, T 2 , a third transistor T 3 , a bit line, BL, a Wordline Write, WLW, a Wordline Read, WLR, and a Wordline-Readline, WLRL;
each of T 1 and T 3 is a metal oxide semiconductor field effect transistor (MOSFET), and T 2 is a FeFET;
T 1 has a T 1 -source, a T 1 -gate, and a T 1 -drain;
T 2 has a T 2 -source, a T 2 -gate, and a T 2 -drain;
T 3 has a T 3 -source, a T 3 -gate, and a T 3 -drain;
T 1 -drain being connected to T 2 -gate;
T 1 -gate being connected to WLW;
T 1 -source being connected to BL;
T 2 -drain being connected to T 3 -drain;
T 2 -gate being connected to T 1 -drain;
T 2 -source being connected to WLRW;
T 3 -drain being connected to T 2 -drain;
T 3 -gate being connected to WLR; and
T 3 -source being connected to BL.
9. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias, wherein:
the circuit topology is configured as a backup and restore circuit (B&R circuit);
the B&R circuit comprising:
a first transistor, M 1 , M 1 having an M 1 -source, an M 1 -gate, and an M 1 -drain;
a second transistor, M 2 , M 2 having an M 2 -source, an M 2 -gate, and an M 2 -drain;
a third transistor, M 3 , M 3 having an M 3 -source, an M 3 -gate, and an M 3 -drain;
a fourth transistor, M 4 , M 4 having an M 4 -source, an M 4 -gate, and an M 4 -drain;
a first branch comprising M 1 , M 3 , and ground, GND;
a second branch comprising M 2 , M 4 , and GND;
each of M 1 and M 2 is a metal oxide semiconductor field effect transistor (MOSFET);
each of M 3 and M 4 is a FeFET;
M 1 -drain being connected to M 3 -source;
M 1 -gate being connected to a restore signal input signal and M 2 -gate;
M 1 -source being connected to GND;
M 2 -drain being connected to M 4 -source;
M 2 -gate being connected to M 1 -gate;
M 3 -drain configured to be connected to a slave latch via the first branch;
M 3 -drain being connected to M 4 -gate, M 4 -drain, M 3 -gate, and to the second branch;
M 3 -gate being connected to M 4 -gate, M 4 -drain, M 3 -drain, and to the second branch;
M 3 -source being connected to M 1 -drain;
M 4 -drain configured to be connected to the slave latch via the second branch;
M 4 -drain being connected to M 3 -gate, M 3 -drain, M 4 -gate, and to the first branch;
M 4 -gate being connected to M 3 -gate, M 3 -drain, M 4 -drain, and to the first branch; and
M 4 -source being connected to M 2 -drain.
10. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias, wherein:
the circuit topology is configured as a D-Flip Flop (DFF);
the DFF comprising a master latch, a slave latch, and a backup and restore circuit (B&R circuit);
the master latch comprising:
a first master inverter M INV1 , a second master inverter, M INV2 , a third master inverter, M INV3 , and a master transmission gate, M GATE ;
input of Mm being connected to a data input signal, D;
output of Mm being connected to input of M INV2 ;
input of M INV2 being connected to output of M INV1 ;
output of M INV2 being connected to input of M INV3 ;
input of M INV3 being connected to output of M INV2 ;
output of M INV3 being connected to input of M GATE ;
input of M GATE being connected to output of M INV3 ; and
output of M GATE being connected to input of M INV2 and output of M INV1 ;
the slave latch comprising:
a first slave inverter, S INV1 , a second slave inverter, S INV2 , a third slave inverter, S INV3 , and a slave transmission gate, S GATE ;
input of S INV1 being connected to output of M INV2 ;
input of S INV2 being connected to output of S INV1 ;
output of S INV2 being connected to input of S INV3 and to a data output Q;
input of S INV3 being connected to output of S INV2 ;
output of S INV3 being connected to input of S GATE ; and
output of S GATE being connected to input of S INV2 and output of S INV1 ; and
the B&R circuit comprising:
a first transistor, M 1 , M 1 having an M 1 -source, an M 1 -gate, and an M 1 -drain;
a second transistor, M 2 , M 2 having an M 2 -source, an M 2 -gate, and an M 2 -drain;
a third transistor, M 3 , M 3 having an M 3 -source, an M 3 -gate, and an M 3 -drain;
a fourth transistor, M 4 , M 4 having an M 4 -source, an M 4 -gate, and an M 4 -drain;
a first branch comprising M 1 , M 3 , and ground, GND;
a second branch comprising M 2 , M 4 , and GND;
each of M 1 and M 2 is a metal oxide semiconductor field effect transistor (MOSFET);
each of M 3 and M 4 is a FeFET;
M 1 -drain being connected to M 3 -source;
M 1 -gate being connected to a restore signal input signal and M 2 -gate;
M 1 -source being connected to GND;
M 2 -drain being connected to M 4 -source;
M 2 -gate being connected to M 1 -gate;
M 3 -drain configured to be connected to a slave latch via the first branch;
M 3 -drain being connected to M 4 -gate, M 4 -drain, M 3 -gate, and to the second branch;
M 3 -gate being connected to M 4 -gate, M 4 -drain, M 3 -drain, and to the second branch;
M 3 -source being connected to M 1 -drain;
M 4 -drain configured to be connected to the slave latch via the second branch;
M 4 -drain being connected to M 3 -gate, M 3 -drain, M 4 -gate, and to the first branch;
M 4 -gate being connected to M 3 -gate, M 3 -drain, M 4 -drain, and to the first branch; and
M 4 -source being connected to M 2 -drain.
11. The NVM device recited in claim 9 , wherein:
M 3 -drain being connected to output of S GATE , output of S INV1 , and input of S INV2 , and
M 4 -drain being connected to input of S INV3 , output of S INV2 , and data output Q.