IP Library › Granted Patent US 10,672,761
Granted Patent B2
US 10,672,761 · App. 16/151,853 · Granted Jun 2, 2020

Semiconductor device

Inventor: Takuya Yoshida (Fukuoka, JP)
Assignee: Mitsubishi Electric Corporation
H01L27/0664H01L29/0623H01L29/1095H01L29/7397H01L29/8613H01L29/16H01L29/1602H01L29/1608H01L29/2003
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Quick Facts
Patent No.
US 10,672,761
App. No.
16/151,853
Granted
Jun 2, 2020
Kind
B2
Abstract

A semiconductor device includes: a semiconductor substrate having a cell region, a termination region located around the cell region, and a wiring region; an IGBT provided in the cell region; an insulating film provided on the semiconductor substrate in the wiring region; a gate electrode provided on the insulating film and connected to a gate of the IGBT; a p-type well layer provided on a surface side of the semiconductor substrate in the termination region; and a diode provided in the wiring region, wherein the diode includes a the p-type base layer provided on the surface side of the semiconductor substrate and an n-type cathode layer provided on a reverse side of the semiconductor substrate, the p-type base layer is provided in common to the wiring region and the cell region and has a lower impurity concentration and a smaller depth than the p-type well layer.

Claims (40)

1. A semiconductor device comprising:

a semiconductor substrate having a cell region, a termination region located around the cell region, and a wiring region;

an IGBT provided in the cell region;

an insulating film provided on the semiconductor substrate in the wiring region;

a gate electrode provided on the insulating film and connected to a gate of the IGBT;

a p-type base layer provided on a surface side of the semiconductor substrate in the cell region and the wiring region;

a p-type well layer provided on a surface side of the semiconductor substrate in the termination region; and

a diode provided in the wiring region, wherein

the diode includes the p-type base layer and an n-type cathode layer provided on a reverse side of the semiconductor substrate,

an impurity concentration of the p-type base layer in the cell region is equal to an impurity concentration of the p-type base layer in the wiring region,

a depth of the p-type base layer in the cell region is equal to a depth of the p-type base layer in the wiring region, and

the p-type base layer has a lower impurity concentration and a smaller depth than the p-type well layer.

2. The semiconductor device according to claim 1 , further comprising:

a p-type emitter layer provided on a surface side of the p-type base layer in the wiring region and having a higher impurity concentration than the p-type base layer; and

a surface electrode connected to the p-type base layer and the p-type emitter layer,

wherein the p-type emitter layer is away from the p-type well layer.

3. The semiconductor device according to claim 2 , wherein the p-type emitter layer is provided in a part connected to the surface electrode.

4. The semiconductor device according to claim 1 , wherein the semiconductor substrate is made of a wide-band-gap semiconductor.

5. The semiconductor device according to claim 2 , wherein the semiconductor substrate is made of a wide-band-gap semiconductor.

6. The semiconductor device according to claim 3 , wherein the semiconductor substrate is made of a wide-band-gap semiconductor.

7. A semiconductor device comprising:

a semiconductor substrate having a cell region, a termination region located around the cell region, and a wiring region;

an IGBT provided in the cell region;

an insulating film provided on the semiconductor substrate in the wiring region;

a gate electrode provided on the insulating film and connected to a gate of the IGBT;

a p-type well layer provided on a surface side of the semiconductor substrate in the termination region; and

a diode provided in the wiring region;

an n-type drift layer provided in the semiconductor substrate between the p-type base layer and the n-type cathode layer, wherein

the p-type well layer is in the wiring region,

a distance as seen in a plan view from the p-type well layer to the n-type cathode layer is equal to or greater than a thickness of the n-type drift layer,

the diode includes a the p-type base layer provided on the surface side of the semiconductor substrate and an n-type cathode layer provided on a reverse side of the semiconductor substrate, and

the p-type base layer is provided in common to the wiring region and the cell region and has a lower impurity concentration and a smaller depth than the p-type well layer.

8. The semiconductor device according to claim 7 , further comprising:

a p-type emitter layer provided on a surface side of the p-type base layer in the wiring region and having a higher impurity concentration than the p-type base layer; and

a surface electrode connected to the p-type base layer and the p-type emitter layer,

wherein the p-type emitter layer is away from the p-type well layer.

9. The semiconductor device according to claim 8 , wherein the p-type emitter layer is provided in a part connected to the surface electrode.

10. The semiconductor device according to claim 7 , wherein the semiconductor substrate is made of a wide-band-gap semiconductor.

11. The semiconductor device according to claim 8 , wherein the semiconductor substrate is made of a wide-band-gap semiconductor.

12. The semiconductor device according to claim 9 , wherein the semiconductor substrate is made of a wide-band-gap semiconductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2018
From: YOSHIDA, TAKUYA
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 047071/0102 →
Priority Claims (1)
JP 2018-079227 · Apr 17, 2018 · national
Continuity (1)
Related Publication 20190319026A1 · Oct 17, 2019
Cited By (1)
US 12,519,074