CMOS image sensor with shallow trench edge doping

1. An integrated chip, comprising:

a photodetector arranged within a semiconductor substrate having a first doping type;

one or more dielectric materials disposed within a trench defined by interior surfaces of the semiconductor substrate;

a doped epitaxial material arranged within the trench at a location laterally between the one or more dielectric materials and the photodetector, wherein the doped epitaxial material has a second doping type that is different than the first doping type; and

wherein the doped epitaxial material protrudes outward from within the trench to over the semiconductor substrate.

2. The integrated chip of claim 1 , further comprising:

a first well region disposed within the semiconductor substrate between the trench and the photodetector, wherein the first well region has the second doping type and a smaller doping concentration than that of the doped epitaxial material.

3. The integrated chip of claim 2 , further comprising:

a floating diffusion region disposed within the semiconductor substrate;

a gate structure disposed over the semiconductor substrate between the photodetector and the floating diffusion region; and

a second well region disposed within the semiconductor substrate and surrounding the floating diffusion region, wherein the second well region has the second doping type and a smaller doping concentration than that of the first well region between the trench and the photodetector.

4. The integrated chip of claim 1 ,

wherein the doped epitaxial material separates the one or more dielectric materials from a first sidewall of the semiconductor substrate defining the trench; and

wherein the one or more dielectric materials separate the doped epitaxial material from a second sidewall of the semiconductor substrate defining the trench.

5. The integrated chip of claim 4 , wherein the doped epitaxial material directly contacts the first sidewall.

6. The integrated chip of claim 1 ,

wherein the photodetector comprises a first region disposed within the semiconductor substrate and having the first doping type;

wherein the doped epitaxial material continuously extends from within the trench to directly above the first region; and

wherein the doped epitaxial material that is directly above the first region defines a second region of the photodetector.

7. The integrated chip of claim 6 , wherein the doped epitaxial material directly contacts an upper surface of the first region.

8. The integrated chip of claim 1 , further comprising:

a dielectric protection layer arranged over the one or more dielectric materials within the trench, wherein the dielectric protection layer laterally contacts a sidewall of the doped epitaxial material.

9. The integrated chip of claim 1 , wherein the doped epitaxial material extends from a bottom of the trench to over the semiconductor substrate.

10. An integrated chip, comprising:

a substrate having interior surfaces defining a trench;

a first well region disposed within the substrate between the trench and a first photodiode region;

a floating diffusion region surrounded by a second well region disposed within the substrate;

a gate structure arranged over the substrate between the first photodiode region and the floating diffusion region;

one or more dielectric materials disposed within the trench; and

a doped epitaxial material arranged within the trench between the one or more dielectric materials and the first well region.

11. The integrated chip of claim 10 , wherein the first well region has a doping concentration that is in a range of between approximately 1×10 15 atoms/cm 3 and approximately 1×10 17 atoms/cm 3 .

12. The integrated chip of claim 10 , wherein the doped epitaxial material continuously extends from within the trench to directly contact a top of the first photodiode region.

13. The integrated chip of claim 10 , wherein the doped epitaxial material has a larger doping concentration than that of the first well region or the second well region.

14. The integrated chip of claim 10 , further comprising:

sidewall spacers arranged along opposing sides of the gate structure, wherein the doped epitaxial material laterally contacts the sidewall spacers.

15. The integrated chip of claim 10 , wherein the substrate has a first doping type, the first well region and the second well region have a second doping type different than the first doping type, the first photodiode region has the first doping type, and the doped epitaxial material has the second doping type.

16. An integrated chip, comprising:

an image sensing element arranged within a substrate;

a gate electrode disposed over an upper surface of the substrate;

one or more dielectric materials disposed within a trench defined by interior surfaces of the substrate; and

a doped epitaxial material arranged within the trench at a location laterally between the one or more dielectric materials and the image sensing element, wherein the doped epitaxial material continuously extends from within the trench to a position directly over the upper surface of the substrate.

17. The integrated chip of claim 16 , further comprising:

one or more sidewall spacers disposed along sidewalls of the gate electrode; and

a dielectric protection layer separating the one or more sidewall spacers from the gate electrode, wherein the doped epitaxial material laterally contacts the dielectric protection layer.

18. The integrated chip of claim 16 , wherein the doped epitaxial material has a lower surface directly over the image sensing element.

19. The integrated chip of claim 16 , wherein the doped epitaxial material directly contacts a horizontally extending surface of the substrate that defines a bottom of the trench.

20. The integrated chip of claim 16 , wherein the doped epitaxial material directly contacts a sidewall of the substrate defining the trench.