Embedded magnetic inductor
An apparatus and method of forming a magnetic inductor circuit. A substrate is provided and a first magnetic layer is formed in contact with one layer of the substrate. A conductive trace is formed in contact with the first magnetic layer. A sacrificial cooper layer protects the magnetic material from wet chemistry process steps. A conductive connection is formed from the conductive trace to the outside substrate, the conductive connection comprising a horizontal connection formed by in-layer plating. A second magnetic layer is formed in contact with the conductive trace. Instead of a horizontal connection, a vertical conductive connection can be formed that is perpendicular to the magnetic layers, by drilling a first via in a second of the magnetic layers, forming a buildup layer, and drilling a second via through the buildup layer, where the buildup layer protects the magnetic layers from wet chemistry processes.
1. A semiconductor circuit comprising:
a substrate that includes a plurality of parallel layers;
a first magnetic material in contact with a first layer of the plurality of parallel layers;
a second magnetic material in contact with a second layer of the plurality of parallel layer;
a conductive trace embedded within one of more of the first magnetic material or the second magnetic material;
a conductive connection from the conductive trace to the outside substrate, the conductive connection comprising a horizontal connection.
2. The semiconductor circuit of claim 1 further comprising a conductive pad spaced horizontally from the conductive trace and in contact with the conductive connection.
3. The semiconductor circuit of claim 1 , wherein conductive trace is contained within the first layer and extends vertically into the first magnetic material from an interface between the first layer and the second layer.
4. The semiconductor circuit of claim 2 wherein the conductive connection between the conductive pad and the outside substrate comprises a solder ball.
5. The semiconductor circuit of claim 2 , wherein the conductive trace, the horizontal connection and the conductive pad are on the same layer.
6. The semiconductor circuit of claim 2 , wherein the one layer comprises a first buildup (BU) layer and the conductive pad is formed on the first BU layer.
7. The semiconductor circuit of claim 6 wherein the first BU layer includes a first cavity and the first magnetic material is in the first cavity.
8. The semiconductor circuit of claim 7 further comprising a solder resist (SR) layer above the first BU layer.
9. The semiconductor circuit of claim 8 wherein the SR layer includes a second cavity and the second magnetic material is in the second cavity.
10. The semiconductor circuit of claim 8 wherein the second magnetic material is in contact with the first magnetic material.
11. The semiconductor circuit of claim 1 , wherein the conductive connection partially overlaps the conductive trace, and the second magnetic material interfaces with the conductive connection, the conductive trace, and the first magnetic material.
12. The semiconductor circuit of claim 7 , wherein a second BU layer is below the SR layer, the second BU layer comprising at least one trace.