Structure and method for high-k metal gate

1. A method of forming a gate dielectric material, the method comprising:

forming an interface material in a first region over a substrate; and

forming a high-K dielectric material having an effective oxide thickness of 0.5 nm or less in the first region over the interface material, wherein forming the high-K dielectric material comprises:

forming a first dielectric layer comprising hafnium oxide;

after forming the first dielectric layer, forming a second dielectric layer comprising hafnium lanthanum oxide directly on the first dielectric layer; and

after forming the second dielectric layer, forming a third dielectric layer comprising lanthanum aluminum oxide directly on the second dielectric layer.

2. The method of claim 1 , wherein forming the interface material comprises:

forming a fourth dielectric layer comprising an oxide of the substrate; and

forming a fifth dielectric layer comprising a hafnium doped material of the fourth dielectric layer, wherein the fifth dielectric layer is between the fourth dielectric layer and the high-K dielectric material.

3. The method of claim 2 , wherein the fourth dielectric layer comprises silicon oxide, and the fifth dielectric layer comprises hafnium silicate.

4. The method of claim 1 , further comprising forming a capping layer comprising titanium silicon nitride over the high-K dielectric material.

5. The method of claim 4 , further comprising performing a first anneal process after forming the capping layer.

6. The method of claim 5 , further comprising:

forming a silicon capping layer over the capping layer;

performing a second anneal process after forming the silicon capping layer; and

removing the silicon capping layer after the second anneal process.

7. The method of claim 1 , wherein forming the high-K dielectric material further comprises forming the high-K dielectric material in a second region over the substrate, wherein the first region is a PMOS region, and the second region is an NMOS region.

8. The method of claim 1 , wherein the thickness of the first dielectric layer is in a range from about 0.5 nm to about 5 nm.

9. A method of forming a Fin Field-Effect (FinFET) device, the method comprising:

removing a first dummy gate of a first gate stack disposed over a first fin in a PMOS region of a substrate;

removing a second dummy gate of a second gate stack disposed over a second fin in an NMOS region of the substrate, wherein removing the first dummy gate and removing the second dummy gate create a first opening in the PMOS region and a second opening in the NMOS region, respectively;

forming an interface dielectric material in the first opening and in the second opening, the interface dielectric material lining bottom surfaces of the first opening and the second opening;

forming a high-K dielectric material having an effective oxide thickness of 0.5 nm or less in the first opening and in the second opening, the high-K dielectric material disposed over the interface dielectric material, comprising forming a hafnium oxide layer, after forming the hafnium oxide layer forming a hafnium lanthanum oxide layer directly on the hafnium oxide layer, and after forming the hafnium lanthanum oxide layer, forming a lanthanum aluminum oxide layer directly on the hafnium lanthanum oxide layer; and

filling the first opening and the second opening with a conductive material, wherein after the filling, the high-K dielectric material is in the first opening and the second opening.

10. The method of claim 9 , further comprising forming a capping layer over the high-K dielectric material in the first opening and in the second opening before filling the first opening and the second opening.

11. The method of claim 10 , further comprising forming a barrier layer over the capping layer, wherein the barrier layer is between the capping layer and the conductive material after the filling.

12. The method of claim 9 , wherein the interface dielectric material is formed in the first opening and the second opening at a same time, and the high-K dielectric material is formed in the first opening and the second opening at a same time.

13. The method of claim 9 , wherein forming the interface dielectric material comprises:

forming a first dielectric layer comprising silicon oxide in the first opening and in the second opening; and

forming a second dielectric layer comprising hafnium silicate over the first dielectric layer in the first opening and in the second opening.

14. The method of claim 9 , wherein the thickness of the hafnium oxide layer is in a range from about 0.5 nm to about 5 nm.

15. The method of claim 9 , wherein the thickness of the hafnium lanthanum oxide layer is in a range from about 0.5 nm to about 2 nm.

16. A method of forming a semiconductor device comprising:

forming a first transistor in a first region of a substrate, where forming the first transistor comprises:

forming a first interface material over the substrate;

forming a first high-K dielectric material having an effective oxide thickness of 0.5 nm or less over the first interface material, wherein forming the first high-K dielectric material comprises:

forming a first dielectric layer comprising hafnium oxide over the substrate;

after forming the first dielectric layer, forming a second dielectric layer comprising hafnium lanthanum oxide directly in contact with the first dielectric layer; and

after forming the second dielectric layer, forming a third dielectric layer comprising lanthanum aluminum oxide directly in contact with the second dielectric layer;

forming a first capping layer over the first high-K dielectric material; and

forming a first gate electrode over the first capping layer.

17. The method of claim 16 , wherein forming the first interface material comprises:

forming a fourth dielectric layer comprising silicon oxide over the substrate; and

forming a fifth dielectric layer comprising hafnium silicate over the fourth dielectric layer.

18. The method of claim 16 , wherein the first capping layer is formed of titanium silicon nitride, tantalum silicon nitride, or hafnium silicon oxynitride.

19. The method of claim 16 , further comprising forming a second transistor in a second region of the substrate, wherein the first transistor is a P-type transistor, and the second transistor is an N-type transistor, wherein forming the second transistor comprises:

forming a second high-K dielectric material over the substrate, wherein the second high-K dielectric material is the same as the first high-K dielectric material;

forming a second capping layer over the second high-K dielectric material; and

forming a second gate electrode over the second capping layer.

20. The method of claim 16 , wherein the thickness of the second dielectric layer is in a range from about 0.5 nm to about 2 nm.