Method of fabricating ferroelectric field-effect transistor
The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.
1. A method of fabricating a ferroelectric field-effect transistor (FeFET), the method comprising:
forming a layer stack on a gate structure, wherein forming the layer stack comprises forming a ferroelectric layer on the gate structure followed by forming a sacrificial stressor layer on the ferroelectric layer;
heat-treating the layer stack to cause a phase transition in the ferroelectric layer;
subsequent to heat-treating, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer; and
forming a source contact and a drain contact contacting the 2D material channel layer.
2. The method according to claim 1 , wherein the sacrificial stressor layer includes a metal layer.
3. The method according to claim 2 , wherein the metal layer includes titanium nitride, tantalum nitride, titanium tantalum nitride or a combination thereof.
4. The method according to claim 1 , wherein the ferroelectric layer includes hafnium oxide, zirconium oxide, hafnium titanate, hafnium zirconium oxide or a combination thereof.
5. The method according to claim 1 , wherein the 2D material channel layer includes one or more mono-layers of a transition metal dichalcogenide material or one or more mono-layers of graphene.
6. The method according to claim 5 , wherein the 2D material channel layer includes one or more mono-layers of WS 2 , WSe 2 , MoS 2 , MoSe 2 , WTe 2 or MoTe 2 .
7. The method according to claim 1 , wherein heat-treating comprises heating the ferroelectric layer at a temperature in a range of 300° C. to 1200° C.
8. The method according to claim 1 , wherein the gate structure is formed on a substrate and has an upper surface extending along a plane parallel to a main surface of the substrate, and wherein the layer stack is formed on the upper surface.
9. The method according to claim 1 , wherein the gate structure is formed on a substrate having a semiconductor structure extending vertically from the substrate, wherein the semiconductor structure has a sidewall surface on which the gate structure is formed.
10. The method according to claim 1 , wherein the gate structure is a sacrificial gate structure and the method further comprises replacing the sacrificial gate structure with a replacement gate structure.
11. The method according to claim 1 , wherein the gate structure comprises a gate electrode.
12. The method according to claim 1 , wherein forming the layer stack further comprises forming a high-K dielectric layer subsequent to forming the ferroelectric layer.
13. A method of fabricating a ferroelectric field effect transistor (FeFET), the method comprising:
forming a metal gate on a substrate;
forming a ferroelectric layer on the metal gate;
forming a sacrificial metal channel layer on the ferroelectric layer;
thermally annealing the ferroelectric layer and the sacrificial metal channel layer at a temperature between 300° C. and 1200° C.; and
replacing the sacrificial metal channel layer with a channel layer formed of a two-dimensional (2D) layered material.
14. The method according to claim 13 , wherein the ferroelectric layer is such that thermally annealing increases a degree of ferroelectricity in the ferroelectric layer.
15. The method according to claim 13 , wherein the ferroelectric layer is such that thermally annealing induces an amorphous-to-crystalline transition in the ferroelectric layer.
16. The method according to claim 13 , wherein the sacrificial metal channel layer is formed of titanium nitride, tantalum nitride, titanium tantalum nitride or a combination thereof.
17. The method according to claim 13 , wherein the ferroelectric layer is formed of hafnium oxide, zirconium oxide, hafnium titanate, hafnium zirconium oxide or a combination thereof.
18. The method according to claim 13 , wherein the 2D layered material comprises a transition metal dichalcogenide or graphene.
19. The method according to claim 13 , wherein the substrate comprises an insulating layer on which the metal gate is formed, and wherein the metal gate is electrically connected by interconnect metallization formed in the insulating layer.
20. The method according to claim 13 , wherein the substrate comprises a fin having sidewalls on which the metal gate is formed.