Resistive memory crossbar array compatible with Cu metallization

1. A method for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array, the method comprising:

forming a plurality of conductive lines within an interlayer dielectric (ILD);

forming a RRAM stack over a conductive line of the plurality of conductive lines, the RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask; and

removing an entirety of a first layer of the bi-layer hardmask during a via opening.

2. The method of claim 1 , further comprising forming a low-k dielectric layer over the RRAM stack before removing the entirety of the first layer of the bi-layer hardmask.

3. The method of claim 2 , further comprising removing a second layer of the bilayer hardmask.

4. The method of claim 3 , wherein the second layer of the bilayer hardmask is removed concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.

5. The method of claim 4 , further comprising forming a barrier layer over the conductive line of the plurality of conductive lines in alignment with the RRAM stack.

6. The method of claim 5 , further comprising forming an encapsulation layer over the RRAM stack.

7. The method of claim 6 , further comprising etching the encapsulation layer to form outer spacers adjacent the RRAM stack.

8. The method of claim 7 , further comprising selectively recessing the plurality of sacrificial layers to create an opening in alignment with the RRAM stack.

9. The method of claim 8 , wherein the plurality of sacrificial layers includes a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer.

10. The method of claim 9 , wherein etch rate differences between the bi-layer hardmask and the outer spacers creates a step-like via landing on the RRAM.

11. A semiconductor structure for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array, the semiconductor structure comprising:

a plurality of conductive lines disposed within an inter-layer dielectric (ILD);

a barrier layer disposed in direct contact with a conductive line of the plurality of conductive lines;

a bottom electrode disposed over the barrier layer;

a high-k dielectric layer disposed over the bottom electrode; and

a top electrode disposed over the high-k dielectric layer.

12. The semiconductor structure of claim 11 , wherein outer spacers are disposed adjacent the bottom electrode, the high-k dielectric layer, and the top electrode.

13. The semiconductor structure of claim 12 , wherein the outer spacers extend vertically beyond a top surface of the top electrode to create a step-like via landing.

14. The semiconductor structure of claim 13 , wherein a conductive material is disposed over the top electrode.

15. The semiconductor structure of claim 14 , wherein the conductive material includes copper (Cu).

16. The semiconductor structure of claim 15 , wherein etch rate differences between a dual layer hardmask and the outer spacers creates the step-like via landing.

17. The semiconductor structure of claim 16 , wherein the step-like via landing is aligned with the bottom electrode, the high-k dielectric layer, and the top electrode.

18. The semiconductor structure of claim 11 , wherein the bottom electrode includes titanium nitride (TiN), the high-k dielectric layer includes hafnium oxide (HfO), and the top electrode includes TiN.

19. The semiconductor structure of claim 11 , wherein the bottom electrode is constructed from the same material as the top electrode.

20. The semiconductor structure of claim 11 , wherein the barrier layer includes tantalum nitride (TaN).