Semiconductor device

1. A semiconductor device comprising:

a semiconductor substrate including a chip region and an edge region around the chip region;

a semiconductor integrated circuit in the chip region of the semiconductor substrate;

first metal patterns and first metal vias electrically connected to the semiconductor integrated circuit;

a lower insulation layer covering the edge region;

a plurality of connection structures in the lower insulating layer and disposed over the edge region, the connection structures spaced from each other by first intervals in a first direction;

an upper insulating layer covering the connection structures; and

a plurality of redistribution pads disposed on the upper insulating layer, each of the redistribution pads being electrically connected to the connection structures, respectively,

wherein the lower insulation layer covers the semiconductor integrated circuit, the first metal patterns, and the first metal vias,

the redistribution pads include pad portions, respectively,

the pad portions of the redistribution pads are located over the chip region, and

the pad portions of the redistribution pads are collectively spaced apart from the connection structures in a second direction intersecting the first direction when viewed in a plan view.

2. The semiconductor device of claim 1 , wherein respective ones of the pad portions of the redistribution pads are disposed adjacent one another as spaced by second intervals in the first direction.

3. The semiconductor device of claim 2 , wherein the first intervals are substantially uniform, the second intervals are substantially uniform and each of the second intervals is substantially equal to or less than each of the first intervals.

4. The semiconductor device of claim 1 , wherein the lower insulating layer comprises a dielectric material having a dielectric constant lower than that of the upper insulating layer, and

each of the connection structures includes second metal patterns and second metal vias alternately stacked with the second metal patterns.

5. The semiconductor device of claim 1 , wherein each of the pad portions of the redistribution pads has a width greater than a width of the connection structure to which it is electrically connected.

6. The semiconductor device of claim 1 , wherein each of the redistribution pads further includes:

a via portion extending through the upper insulating layer on the edge region and into contact with one of the connection structures; and

a line-shaped portion extending lengthwise in the second direction on a top surface of the upper insulating layer and connecting the via portion to the pad portion.

7. The semiconductor device of claim 1 , wherein the chip region includes a first pad region spaced from the edge region, and a second pad region adjacent to the edge region so as to be located between the first pad region and edge region, and

the redistribution pads are located over the second pad region, and

further comprising:

redistribution chip pads disposed on the upper insulating layer and located over the first pad region.

8. The semiconductor device of claim 1 ,

further comprising:

a redistribution dummy pad disposed on the chip region and spaced apart from one of the redistribution pads by one of the first intervals, the redistribution dummy pad comprising a dummy via portion disposed in the upper insulating layer, a dummy pad portion disposed on a top surface of the upper insulating layer and located over the chip region, and a dummy line portion extending in the second direction on the top surface of the upper insulating layer and connecting the dummy via portion to the dummy pad portion, the dummy via portion is having a bottom surface contacting the upper insulating layer.

9. A semiconductor device comprising:

a semiconductor substrate having a chip region and an edge region around the chip region;

a lower insulating layer disposed on the semiconductor substrate;

a plurality of connection structures in the lower insulating layer, located over the edge region of the semiconductor substrate, and spaced from each other by first intervals in a first direction;

an upper insulating layer disposed on the lower insulating layer and covering the connection structures; and

redistribution pads disposed on the upper insulating layer and electrically connected to the connection structures, respectively,

wherein each of the redistribution pads includes:

a via portion extending vertically in the upper insulating layer, located over the edge region and by which the redistribution pad is electrically connected to one of the connection structures;

a pad portion disposed on the upper insulating layer and located over the chip region; and

a line-shaped portion extending in a second direction intersecting the first direction on a top surface of the upper insulating layer and electrically connecting the via portion to the pad portion,

wherein the via portion has a width less than a width of said one of the connection structures, the pad portion has a width greater than the width of the via portion, and the line-shaped portion has a width less than the width of the pad portion.

10. The semiconductor device of claim 9 , wherein the width of the line-shaped portion is equal to or greater than the width of the via portion.

11. The semiconductor device of claim 9 , wherein the lower insulating layer includes a dielectric material whose dielectric constant is lower than that of the upper insulating layer.

12. The semiconductor device of claim 9 , wherein each of the connection structures includes first metal patterns and first metal vias alternately stacked with the first metal patterns, and

the redistribution pads are of metal material different from that of the connection structures.

13. The semiconductor device of claim 9 , wherein respective ones of the pad portions of the redistribution pads are disposed adjacent one another as spaced from each other by second intervals in the first direction,

the first intervals are substantially uniform,

the second intervals are substantially uniform, and

each of the second intervals is substantially equal to or less than each of the first intervals.

14. The semiconductor device of claim 9 , wherein each one of the pad portions of the redistribution pads is spaced apart in the second direction from the connection structure to which it is electrically connected by the same distance as each other of the pad portions is spaced apart in the second direction from the connection structure to which it is electrically connected, when viewed in a plan view.

15. A semiconductor device article of manufacture for singulating into a plurality of chip, comprising:

a semiconductor substrate having an array of chip regions and a scribe lane region in between the chip regions, the scribe lane region including a cutting region and an edge region directly adjacent to the chip regions so as to be located between the cutting region and the chip regions;

integrated circuits in the chip regions of the semiconductor substrate, respectively,

test circuits, configured to test the integrated circuits, in the scribe lane region of the semiconductor substrate;

lower device insulation extending over the chip regions and edge region of the semiconductor substrate;

upper device insulation extending over the lower device insulation;

connection structures extending through the lower device insulation and electrically connected to the test circuits; and

a plurality of redistribution pads electrically connected to the connection structures so as to be electrically connected to the test circuits via the connection structures,

wherein the plurality of redistribution pads includes a respective array of conductive pads located over each of a plurality of the chip regions of the semiconductor substrate as disposed on the upper device insulation, whereby the test circuits can be accessed using the conductive pads, and

each of the redistribution pads extends from a respective one of the chip regions to at least the edge region of the scribe lane region as viewed in a plan view.

16. The semiconductor device article of manufacture of claim 15 , wherein the conductive pads of each respective array are spaced relative to each other each in a first direction,

each of the redistribution pads includes a respective one of the conductive pads, a conductive line-shaped portion extending lengthwise in a second direction, intersecting the first direction, from the respective one of the conductive pads and a conductive via extending vertically in the upper device insulation from the conductive line-shaped portion.

17. The semiconductor device article of manufacture of claim 16 , further comprising redistribution dummy pads spaced apart from the redistribution pads and electrically isolated from the integrated circuits and the test circuits,

wherein each of the redistribution dummy pad comprises a dummy conductive pad disposed on a top surface of the upper device insulation and located over one of the chip regions, a dummy conductive line-shaped portion extending lengthwise from the dummy conductive pad, and a dummy conductive via extending vertically in the upper device insulation from the dummy conductive line-shaped portion.

18. The semiconductor device article of manufacture of claim 15 , wherein the lower device insulation comprises a layer of low-k dielectric material, and further comprising:

internal redistribution interconnection structures disposed in the lower device insulation and electrically connected to the integrated circuits, respectively; and

arrays of redistribution chip pads exposed at an upper surface of the upper device insulation,

each of the arrays of redistribution chip pads being located over a respective one of the chip regions of the semiconductor substrate as spaced from the redistribution pads having the array of conductive pads located over said respective one of the chip regions, and

each of the arrays of redistribution chip pads being electrically connected to a respective one of the internal redistribution interconnection structures so as to be electrically connected to the integrated circuit to which the respective one of the internal redistribution interconnection structures is electrically connected.